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CS42L55
Ultra Low Power, Stereo CODEC w/Class H Headphone Amp
DIGITAL to ANALOG FEATURES
5 mW Stereo Playback Power Consumption 99 dB Dynamic Range (A-wtd) -86 dB THD+N Digital Signal Processing Engine - Bass & Treble Tone Control, De-Emphasis - Master Volume Control (+12 to -102 dB in 0.5 dB steps) - Soft-Ramp & Zero-Cross Transitions - Programmable Peak-Detect and Limiter - Beep Generator w/Full Tone Control
ANALOG to DIGITAL FEATURES
3.5 mW Stereo Record Power Consumption 95 dB Dynamic Range (A-wtd) -87 dB THD+N 2:1 Stereo Input MUX Analog Programmable Gain Amplifier (PGA) (+12 to -6 dB in 0.5 dB steps) +20 dB Boost Programmable Automatic Level Control (ALC) - Noise Gate for Noise Suppression - Programmable Threshold & Attack/Release Rates Independent ADC Channel Control Digital Vol. Ctl. (0 to -96 dB in 1 dB steps) High-Pass Filter Disable for DC Measurements Pseudo Differential Inputs
Stereo Headphone and Line Amplifiers
Step-Down/Inverting Charge Pump Class H Amplifier - Automatic Supply Adj. - High Efficiency - Low EMI Pseudo-Differential Ground-Centered Outputs High HP Power Output at -75 dB THD+N - 2 x 20 mW Into 32 @1.8 V - 2 x 20 mW Into 16 @1.8 V 1 VRMS Line Output @1.8 V Analog Vol. Ctl. (+12 to -55 dB in 1 dB steps) Analog In to Analog Out Passthrough Pop and Click Suppression
+1.65 V to +2.71 V Analog/Digital Supply
LDO Regulator
SYSTEM FEATURES
12 MHz USB Master Clock Input Low Power Operation - Stereo Anlg. Passthrough: 3.3 mW @1.8 V - Stereo Rec. and Playback: 8.3 mW @1.8 V Headphone Detect Input
(SYSTEM FEATURES continued on page 2)
+1.65 V to +2.71 V Charge Pump Supply
Step-Down +VHP Inverting
-VHP
Left 1
Pseudo Diff. Input
ALC
Beep
Mono mix, Limiter, Bass, Treble Adjust Multi-bit
Left HP Output
Pseudo Diff. Input
Right 1 Left 2
Pseudo Diff. Input
ADC
Multi-bit
Attenuator, Boost, Mix
DAC
Ground-Centered Amplifiers
Right HP Output Left Line Output
Pseudo Diff. Input
Right 2 ALC Control Port HPF Serial Audio Port
Level Shifter
Right Line Output Headphone Detect
+1.65 V to +3.47 V Interface Supply
I C Control
2
IS Serial Audio Input/Output
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2007 (All Rights Reserved)
NOVEMBER '07 DS773F1
CS42L55
SYSTEM FEATURES
High Performance 24-bit Converters - Multi-bit Delta Sigma Architecture Integrated High Efficient Power Management Reduces Power Consumption - Step-Down Charge Pump Improves Efficiency - Inverting Charge Pump Accommodates Low System Voltage by Providing Negative Rail for HP/Line Amp - LDO Reg. Provides Low Digital Supply Voltage Digital Power Reduction - Very Low Oversampling Rate for Converters - Bursted Serial Clock Providing 24 Bits per Sample Power Down Management - ADC, DAC, CODEC, PGA, DSP Analog & Digital Routing/Mixes - Line/Headphone Out = Analog In (ADC Bypassed) - Line/Headphone Out = ADC Out - Internal Digital Loopback - Mono Mixes IC(R) Control Port IS Digital Interface Format Flexible Clocking Options - Master or Slave Operation - High-Impedance Digital Output Select (used for easy MUXing between CODEC and other data sources) - 8.000, 11.029, 12.000, 16.000, 22.059, 24.000, 32.000, 44.118 and 48.000 kHz Sample Rates
GENERAL DESCRIPTION
The CS42L55 is a highly integrated, 24-bit, ultra-low power stereo CODEC based on multi-bit delta-sigma modulation. Both the ADC and DAC offer many features suitable for low power portable system applications. The analog input path allows independent channel control of a variety of features. The Programmable Gain Amplifier (PGA) provides analog gain with zero cross transitions. The ADC path includes a digital volume attenuator with soft ramp transitions and a programmable ALC and noise gate monitor the input signals and adjust the volume appropriately. An analog passthrough also exists, accommodating a lower noise, lower power analog in to analog out path to the headphone and line amplifiers, bypassing the ADC and DAC. The DAC output path includes a fixed-function digital signal processing engine. Tone control provides bass and treble adjustment at four selectable corner frequencies. The digital mixer provides independent volume control for both the ADC output and PCM input signal paths, as well as a master volume control. Digital volume controls may be configured to change on soft ramp transitions while the analog controls can be configured to occur on every zero crossing. The DAC path also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The Class H stereo headphone amplifier combines the efficiency of an integrated step-down and inverting charge pump with the linearity and low EMI of a Class AB amplifier. A step-down/inverting charge pump operates in two modes: +/-VCP mode or +/-(VCP/2) mode. Based on the amplifier's output signal, internal logic automatically adjusts the output of the charge pump, +VHPFILT and -VHPFILT, to optimize efficiency. With these features, the amplifier delivers a ground-centered output with a large signal swing even at low voltages and eliminates the need for external DC-blocking capacitors. These features make the CS42L55 the ideal solution for portable applications that require extremely low power consumption in a minimal amount of space. The CS42L55 is available in a 36-pin QFN package for the Commercial (-40C to +85C) grade. The CDB42L55 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 73 for complete details.
APPLICATIONS
HDD & Flash-Based Portable Audio Players MD Players/Recorders PDAs Personal Media Players Portable Game Consoles Digital Voice Recorders Digital Camcorders Digital Cameras Smart Phones
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TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 8 1.1 I/O Pin Characteristics ...................................................................................................................... 9 2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 10 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 RECOMMENDED OPERATING CONDITIONS ................................................................................... 11 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11 ANALOG INPUT CHARACTERISTICS ................................................................................................ 12 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 13 HP OUTPUT CHARACTERISTICS ...................................................................................................... 14 LINE OUTPUT CHARACTERISTICS ................................................................................................... 15 ANALOG PASSTHROUGH CHARACTERISTICS ............................................................................... 16 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 17 SWITCHING SPECIFICATIONS - CONTROL PORT .......................................................................... 18 POWER SUPPLY REJECTION (PSRR) CHARACTERISTICS ........................................................... 19 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 19 POWER CONSUMPTION - ALL SUPPLIES = 1.8 V ............................................................................ 20 POWER CONSUMPTION - ALL SUPPLIES = 2.5 V ............................................................................ 21 4. APPLICATIONS ................................................................................................................................... 22 4.1 Overview ......................................................................................................................................... 22 4.1.1 Basic Architecture ................................................................................................................. 22 4.1.2 Line Inputs ............................................................................................................................. 22 4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers) ................................. 22 4.1.4 Fixed-Function DSP Engine .................................................................................................. 22 4.1.5 Beep Generator ..................................................................................................................... 22 4.1.6 Power Management .............................................................................................................. 22 4.2 Analog Inputs ................................................................................................................................. 23 4.2.1 Pseudo-Differential Inputs ..................................................................................................... 24 4.2.2 Automatic Level Control (ALC) .............................................................................................. 24 4.3 Analog In to Analog Out Passthrough ............................................................................................ 25 4.4 Analog Outputs .............................................................................................................................. 26 4.5 Class H Amplifier ............................................................................................................................ 27 4.5.1 Power Control Options .......................................................................................................... 27 4.5.1.1 Standard Class AB Operation (Mode 01 and 10) ...................................................... 28 4.5.1.2 Adapted to Volume Settings (Mode 00) ..................................................................... 28 4.5.1.3 Adapted to Output Signal (Mode 11) ......................................................................... 29 4.5.2 Power Supply Transitions ...................................................................................................... 29 4.5.3 Efficiency ............................................................................................................................... 31 4.6 Beep Generator .............................................................................................................................. 31 4.7 Limiter ............................................................................................................................................. 32 4.8 Serial Port Clocking ........................................................................................................................ 34 4.9 Digital Interface Format .................................................................................................................. 34 4.10 Initialization ................................................................................................................................... 34 4.11 Recommended DAC to HP or Line Power-Up Sequence (Playback) .......................................... 35 4.11.1 Recommended Power-Down Sequence ............................................................................. 36 4.12 Recommended PGA to HP or Line Power-Up Sequence (Analog Passthrough) ......................... 36 4.12.1 Recommended Power-Down Sequence ............................................................................. 36 4.13 Required Initialization Settings ..................................................................................................... 37 4.14 Control Port Operation .................................................................................................................. 38 4.14.1 IC Control ........................................................................................................................... 38 4.14.2 Memory Address Pointer (MAP) .......................................................................................... 39 4.14.2.1 Map Increment (INCR) ............................................................................................. 39 DS773F1 3
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5. REGISTER QUICK REFERENCE ........................................................................................................ 40 6. REGISTER DESCRIPTION .................................................................................................................. 42 6.1 Fab I.D. and Revision Register (Address 01h) (Read Only) ........................................................... 42 6.1.1 Chip Revision (Read Only) .................................................................................................... 42 6.2 Power Control 1 (Address 02h) ...................................................................................................... 42 6.2.1 Power Down ADC Charge Pump .......................................................................................... 42 6.2.2 Power Down ADC x ............................................................................................................... 42 6.2.3 Power Down .......................................................................................................................... 42 6.3 Power Control 2 (Address 03h) ...................................................................................................... 43 6.3.1 Headphone Power Control .................................................................................................... 43 6.3.2 Line Power Control ................................................................................................................ 43 6.4 Clocking Control 1 (Address 04h) ................................................................................................... 43 6.4.1 Master/Slave Mode ............................................................................................................... 43 6.4.2 SCLK Polarity ........................................................................................................................ 43 6.4.3 SCLK Equals MCLK .............................................................................................................. 44 6.4.4 MCLK Divide By 2 ................................................................................................................. 44 6.4.5 MCLK Disable ....................................................................................................................... 44 6.5 Clocking Control 2 (Address 05h) ................................................................................................... 44 6.5.1 Speed Mode .......................................................................................................................... 44 6.5.2 32 kHz Sample Rate Group .................................................................................................. 45 6.5.3 Internal MCLK/LRCK Ratio ................................................................................................... 45 6.6 Class H Power Control (Address 06h) ............................................................................................ 45 6.6.1 Adaptive Power Adjustment .................................................................................................. 45 6.7 Miscellaneous Control (Address 07h) ............................................................................................. 45 6.7.1 Digital MUX ........................................................................................................................... 45 6.7.2 Analog Zero Cross ................................................................................................................ 46 6.7.3 Digital Soft Ramp .................................................................................................................. 46 6.7.4 Freeze Registers ................................................................................................................... 46 6.8 ADC, Line, HP MUX (Address 08h) ................................................................................................ 46 6.8.1 ADC x Input Select ................................................................................................................ 46 6.8.2 Line Input Select .................................................................................................................... 47 6.8.3 Headphone Input Select ........................................................................................................ 47 6.9 HPF Control (Address 09h) ............................................................................................................ 47 6.9.1 ADCx High-Pass Filter .......................................................................................................... 47 6.9.2 ADCx High-Pass Filter Freeze .............................................................................................. 47 6.9.3 HPF x Corner Frequency ...................................................................................................... 47 6.10 Misc. ADC Control (Address 0Ah) ................................................................................................ 48 6.10.1 ADC Channel B=A .............................................................................................................. 48 6.10.2 PGA Channel B=A .............................................................................................................. 48 6.10.3 Digital Sum .......................................................................................................................... 48 6.10.4 Invert ADC Signal Polarity ................................................................................................... 48 6.10.5 ADC Mute ............................................................................................................................ 48 6.11 PGA x MUX, Volume: PGA A (Address 0Bh) & PGA B (Address 0Ch) ................................................................................... 49 6.11.1 Boostx ................................................................................................................................. 49 6.11.2 PGA x Input Select .............................................................................................................. 49 6.11.3 PGAx Volume ...................................................................................................................... 49 6.12 ADCx Attenuator Control: ADCAATT (Address 0Dh) & ADCBATT (Address 0Eh) ....................................................................... 50 6.12.1 ADCx Volume ...................................................................................................................... 50 6.13 Playback Control 1 (Address 0Fh) ................................................................................................ 50 6.13.1 Power Down DSP ................................................................................................................ 50 6.13.2 HP/Line De-Emphasis ......................................................................................................... 50 6.13.3 Playback Channels B=A ...................................................................................................... 50 4 DS773F1
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6.13.4 Invert PCM Signal Polarity .................................................................................................. 51 6.13.5 Master Playback Mute ......................................................................................................... 51 6.14 ADCx Mixer Volume: ADCA (Address 10h) & ADCB (Address 11h) ...................................................................................... 51 6.14.1 ADC Mixer Channel x Mute ................................................................................................. 51 6.14.2 ADC Mixer Channel x Volume ............................................................................................. 51 6.15 PCMx Mixer Volume: PCMA (Address 12h) & PCMB (Address 13h) ..................................................................................... 52 6.15.1 PCM Mixer Channel x Mute ................................................................................................ 52 6.15.2 PCM Mixer Channel x Volume ............................................................................................ 52 6.16 Beep Frequency & On Time (Address 14h) ................................................................................. 53 6.16.1 Beep Frequency .................................................................................................................. 53 6.16.2 Beep On Time ..................................................................................................................... 54 6.17 Beep Volume & Off Time (Address 15h) ...................................................................................... 54 6.17.1 Beep Off Time ..................................................................................................................... 54 6.17.2 Beep Volume ....................................................................................................................... 55 6.18 Beep & Tone Configuration (Address 16h) ................................................................................... 55 6.18.1 Beep Configuration .............................................................................................................. 55 6.18.2 Treble Corner Frequency .................................................................................................... 55 6.18.3 Bass Corner Frequency ...................................................................................................... 56 6.18.4 Tone Control Enable ........................................................................................................... 56 6.19 Tone Control (Address 17h) ......................................................................................................... 56 6.19.1 Treble Gain .......................................................................................................................... 56 6.19.2 Bass Gain ............................................................................................................................ 56 6.20 Master Volume Control: MSTA (Address 18h) & MSTB (Address 19h) ...................................................................................... 57 6.20.1 Master Volume Control ........................................................................................................ 57 6.21 Headphone Volume Control: HPA (Address 1Ah) & HPB (Address 1Bh) .......................................................................................... 57 6.21.1 Headphone Channel x Mute ................................................................................................ 57 6.21.2 Headphone Volume Control ................................................................................................ 57 6.22 Line Volume Control: LINEA (Address 1Ch) & LINEB (Address 1Dh) .................................................................................... 58 6.22.1 Line Channel x Mute ........................................................................................................... 58 6.22.2 Line Volume Control ............................................................................................................ 58 6.23 Analog Input Advisory Volume (Address 1Eh) ............................................................................. 59 6.23.1 Analog Input Advisory Volume ............................................................................................ 59 6.24 Digital Input Advisory Volume (Address 1Fh) ............................................................................... 59 6.24.1 Digital Input Advisory Volume ............................................................................................. 59 6.25 ADC & PCM Channel Mixer (Address 20h) .................................................................................. 60 6.25.1 PCM Mix Channel Swap ..................................................................................................... 60 6.25.2 ADC Mix Channel Swap ...................................................................................................... 60 6.26 Limiter Min/Max Thresholds (Address 21h) .................................................................................. 60 6.26.1 Limiter Maximum Threshold ................................................................................................ 60 6.26.2 Limiter Cushion Threshold .................................................................................................. 61 6.27 Limiter Control, Release Rate (Address 22h) ............................................................................... 61 6.27.1 Peak Detect and Limiter ...................................................................................................... 61 6.27.2 Peak Signal Limit All Channels ........................................................................................... 61 6.27.3 Limiter Release Rate ........................................................................................................... 62 6.28 Limiter Attack Rate (Address 23h) ................................................................................................ 62 6.28.1 Limiter Attack Rate .............................................................................................................. 62 6.29 ALC Enable & Attack Rate (Address 24h) .................................................................................... 62 6.29.1 ALCx .................................................................................................................................... 62 6.29.2 ALC Attack Rate .................................................................................................................. 63 DS773F1 5
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6.30 ALC Release Rate (Address 25h) ................................................................................................ 63 6.30.1 ALC Release Rate ............................................................................................................... 63 6.31 ALC Threshold (Address 26h) ...................................................................................................... 64 6.31.1 ALC Maximum Threshold .................................................................................................... 64 6.31.2 ALC Minimum Threshold ..................................................................................................... 64 6.32 Noise Gate Control (Address 27h) ............................................................................................... 64 6.32.1 Noise Gate All Channels ..................................................................................................... 64 6.32.2 Noise Gate Enable .............................................................................................................. 65 6.32.3 Noise Gate Threshold and Boost ........................................................................................ 65 6.32.4 Noise Gate Delay Timing .................................................................................................... 65 6.33 ALC and Limiter Soft Ramp, Zero Cross Disables (Address 28h) ................................................ 65 6.33.1 ALCx Soft Ramp Disable ..................................................................................................... 65 6.33.2 ALCx Zero Cross Disable .................................................................................................... 65 6.33.3 Limiter Soft Ramp Disable ................................................................................................... 66 6.34 Status (Address 29h) (Read Only) ............................................................................................... 66 6.34.1 HPDETECT Pin Status (Read Only) ................................................................................... 66 6.34.2 Serial Port Clock Error (Read Only) .................................................................................... 66 6.34.3 DSP Engine Overflow (Read Only) ..................................................................................... 66 6.34.4 MIXx Overflow (Read Only) ................................................................................................. 66 6.34.5 ADCx Overflow (Read Only) ............................................................................................... 67 6.35 Charge Pump Frequency (Address 2Ah) ..................................................................................... 67 6.35.1 Charge Pump Frequency .................................................................................................... 67 7. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 68 7.1 Power Supply ................................................................................................................................. 68 7.2 Grounding ....................................................................................................................................... 68 7.3 QFN Thermal Pad .......................................................................................................................... 68 8. ANALOG VOLUME NON-LINEARITY (DNL & INL) ............................................................................ 69 9. ADC & DAC DIGITAL FILTERS .......................................................................................................... 70 10. PARAMETER DEFINITIONS .............................................................................................................. 71 11. PACKAGE DIMENSIONS .................................................................................................................. 72 THERMAL CHARACTERISTICS .......................................................................................................... 72 12. ORDERING INFORMATION .............................................................................................................. 73 13. REFERENCES .................................................................................................................................... 73 14. REVISION HISTORY .......................................................................................................................... 73
LIST OF FIGURES
Figure 1.Typical Connection Diagram ....................................................................................................... 10 Figure 2.CMRR Test Configuration ........................................................................................................... 12 Figure 3.HP Output Test Configuration ..................................................................................................... 15 Figure 4.Line Output Test Configuration ................................................................................................... 15 Figure 5.Serial Port Timing (Slave Mode) ................................................................................................. 17 Figure 6.Serial Port Timing (Master Mode) ............................................................................................... 17 Figure 7.IC Control Port Timing ............................................................................................................... 18 Figure 8.Power Consumption Test Configuration ..................................................................................... 19 Figure 9.Analog Input Signal Flow ............................................................................................................ 23 Figure 10.Stereo Pseudo-Differential Input ............................................................................................... 24 Figure 11.ALC Operation .......................................................................................................................... 25 Figure 12.DSP Engine Signal Flow ........................................................................................................... 26 Figure 13.Analog Output Stage ................................................................................................................. 27 Figure 14.Adaptive Mode 00 ..................................................................................................................... 28 Figure 15.VHPFILT Transitions ................................................................................................................. 30 Figure 16.VHPFILT Hysteresis ................................................................................................................. 30 Figure 17.Class H Power to Load vs. Power from VCP Supply ................................................................ 31 6 DS773F1
CS42L55
Figure 18.Beep Configuration Options ...................................................................................................... 32 Figure 19.Peak Detect & Limiter ............................................................................................................... 33 Figure 20.IS Format ................................................................................................................................. 34 Figure 21.Control Port Timing, IC Write ................................................................................................... 38 Figure 22.Control Port Timing, IC Read ................................................................................................... 38 Figure 23.PGA Step Size vs. Volume Setting ........................................................................................... 69 Figure 24.PGA Output Volume vs. Volume Setting .................................................................................. 69 Figure 25.HP/Line Step Size vs. Volume Setting ...................................................................................... 69 Figure 26.HP/Line Output Volume vs. Volume Setting ............................................................................. 69 Figure 27.ADC Passband Ripple .............................................................................................................. 70 Figure 28.ADC Stopband Rejection .......................................................................................................... 70 Figure 29.ADC Transition Band ................................................................................................................ 70 Figure 30.ADC Transition Band Detail ...................................................................................................... 70 Figure 31.DAC Passband Ripple .............................................................................................................. 70 Figure 32.DAC Stopband .......................................................................................................................... 70 Figure 33.DAC Transition Band ................................................................................................................ 70 Figure 34.DAC Transition Band (Detail) .................................................................................................... 70
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CS42L55 1. PIN DESCRIPTIONS
HPDETECT
29
SDOUT VL
VDFILT
RESET
30
MCLK
SCLK
36
35
34
33
32
31
SDIN LRCK SDA SCL VCP FLYP +VHPFILT FLYC FLYN
AIN1B
28 27 26 25 24
VLDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
AIN1REF AIN1A AIN2B AIN2REF AIN2A AFILTB AFILTA VQ FILT+
GND/Thermal Pad
23 22 21
Top-Down (Through Package) View
20 19
-VHPFILT
HPOUTA
LINEREF
HPOUTB
LINEOUTA
LINEOUTB
HPREF
Pin Name
SDIN LRCK SDA SCL VCP FLYP +VHPFILT FLYC FLYN -VHPFILT HPOUTA HPOUTB HPREF LINEOUTA LINEOUTB LINEREF
#
1 2 3 4 5 6 7 8 9 10 11 13 12 14 16 15
Pin Description
Serial Audio Data Input (Input) - Input for two's complement serial audio data. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data lines. Serial Control Data (Input/Output) - Serial data for the IC serial control port. Serial Control Port Clock (Input) - Serial clock for the IC serial control port. Step-Down Charge Pump Power (Input) - Power supply for the step-down charge pump. Charge Pump Cap Positive Node (Output) - Positive node for the step-down charge pump's flying capacitor. Step-Down Charge Pump Filter Connection (Output) - Power supply from the step-down charge pump that provides the positive rail for the headphone and line amplifiers Charge Pump Cap Common Node (Output) - Common positive node for the step-down and inverting charge pumps' flying capacitors. Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump's flying capacitor. Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the headphone and line amplifiers. Headphone Audio Output (Output) - The full-scale output level is specified in the HP Output Characteristics specification table Pseudo Diff. Headphone Output Reference (Input) - Ground reference for the headphone amplifiers Line Audio Output (Output) - The full-scale output level is specified in the Line Output Characteristics specification table Pseudo Diff. Line Output Reference (Input) - Ground reference for the line amplifiers.
8
AGND
VA
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VA AGND FILT+ VQ AFILTA AFILTB AIN2A AIN2B AIN1A AIN1B AIN2REF AIN1REF HPDETECT RESET VLDO VDFILT VL SDOUT MCLK SCLK GND/ Thermal Pad 17 18 19 20 21 22 23 25 26 28 24 27 29 30 31 32 33 34 35 36 Analog Power (Input) - Power supply for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage. Antialias Filter Connection (Output) - Antialias filter connection for the ADC inputs. Analog Input (Input) - The full-scale level is specified in the Analog Input Characteristics specification table. Pseudo Diff. Analog Input Reference (Input) - Ground reference for the programmable gain amplifiers (PGA). Headphone Detect (Input) - Powers down the left and/or right channel of the line and/or headphone outputs as described in "Headphone Power Control" on page 43 and "Line Power Control" on page 43. Reset (Input) - The device enters a low power mode when this pin is driven low. Low Dropout Regulator (LDO) Power (Input) - Power supply for the LDO regulator. Low Dropout Regulator (LDO) Filter Connection (Output) - Power supply from the LDO regulator that provides the low voltage power to the digital section. Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and IC control port. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Master Clock (Input) - Clock source for the delta-sigma modulators. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Ground reference for the internal charge pump and digital section; thermal relief pad. See "QFN Thermal Pad" on page 68 for more information.
1.1
I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels should not exceed the corresponding power supply voltage.
Power Supply
Pin Name RESET SCL SDA MCLK
I/O Input Input Input/Output Input Input/Output Input/Output Output Input Input
VL
LRCK SCLK SDOUT SDIN HPDETECT
VA
Internal Connections Weak Pull-up (~1 M) Weak Pull-up (~1 M) -
Driver CMOS/Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS -
Receiver 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 2.5 V, with Hysteresis
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CS42L55 2. TYPICAL CONNECTION DIAGRAM
1 F ** ** 0.1 F ** 0.1 F
+1.65 V to +2.71 V
VDFILT +VHPFILT
2.2 F **
VLDO
VA
47 k
HPREF
0.1 F
HPOUTB
Note 1
**
33
+1.65 V to +2.71 V
2.2 F
VCP
**
HPOUTA
**
0.1 F
33
Headphone Out Left & Right
HPDETECT
CS42L55
Note 2 2.2 F ** 2.2 F **
FLYP FLYC FLYN LINEREF LINEOUTA
562 3300 pF *
LPF is Optional Rext Rext
Note 1 2.2 F
LINEOUTB -VHPFILT
* 3300 pF 562
Line Level Out Left & Right
**
AIN1A MCLK SCLK LRCK Digital Audio Processor SDIN SDOUT RESET SCL SDA AIN2REF AIN2B
1 F
Note 4 1800 pF 1 F
**
1 F 100 100 k
* *
AIN1REF AIN1B
**
1800 pF
**
1 F
100
100 k
Analog Input 1
AIN2A
**
1800 pF
Note 5 100
* *
1 F
100 k 100 k
Analog Input 2
**
1800 pF
**
1 F
100
2 k
2 k
Note 3
AGND +1.65 V to +3.47 V
**
0.1 F
VL AFILTA AFILTB VQ FILT+
*
1000 pF
*
1000 pF
**
2.2 F
**
2.2 F
GND/Thermal Pad
* NPO/C0G dielectric capacitors. ** Low ESR, X7R/X5R dielectric capacitors.
Notes: 1. The headphone amplifier's output power and distortion are rated using the nominal capacitance shown. Larger capacitance reduces the ripple on the internal amplifiers' supplies and in turn reduces the amplifier's distortion at high output power levels. Smaller capacitance may not sufficiently reduce ripple to achieve the rated output power and distortion. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the manufacturer's data sheet, capacitors should be selected based on the minimum output power and maximum distortion required. 2. The headphone amplifier's output power and distortion are rated using the nominal capacitance shown and using the default charge pump switching frequency. The required capacitance follows an inverse relationship with the charge pump's switching frequency. When increasing the switching frequency, the capacitance may decrease; when lowering the switching frequency, the capacitance must increase. Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a percentage specified in the manufacturer's data sheet, capacitors should be selected based on the minimum output power, maximum distortion and maximum charge pump switching frequency required. 3. Additional bulk capacitance may be added to improve PSRR at low frequencies. 4. These capacitors serve as a charge reservoir for the internal switched capacitor ADC modulators and should be placed as close as possible to the inputs. They are only needed when the PGA (Programmable Gain Amplifier) is bypassed. 5. Input pairs (such as AIN2A, AIN2REF and AIN2B) may be left floating if they are not used.
Figure 1. Typical Connection Diagram
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CS42L55 3. CHARACTERISTIC AND SPECIFICATION TABLES RECOMMENDED OPERATING CONDITIONS
GND = AGND = 0 V, all voltages with respect to ground.
Parameters
DC Power Supply Analog Charge Pump LDO Regulator for Digital Serial/Control Port Interface Ambient Temperature
Symbol
VA VCP VLDO VL TA
Min
1.65 1.65 1.65 1.65 -40
Max
2.71 VA 2.71 3.47 +85
Units
V V V V C
Commercial - CNZ
ABSOLUTE MAXIMUM RATINGS
GND = AGND = 0 V; all voltages with respect to ground.
Parameters
DC Power Supply Input Current Analog Input Voltage Digital Input Voltage
Symbol
Min
Max
3.0 4.0 10 VA+0.7 VL+0.4 +115 +150
Units
V V mA V V C C
-0.3 Analog, Charge Pump, LDO VA, VCP, VLDO VL -0.3 Serial/Control Port Interface Iin (Note 2) AGND-0.7 (Note 3) VIN -0.3 VIND (Note 3) TA Tstg -50 -65
Ambient Operating Temperature (power applied) Storage Temperature
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Due to the existence of parasitic body diodes between VCP and VA, current flows from VCP to VA whenever the VA power supply is lower than VCP. This causes a "back-powering" effect on the VA power supply rails internal to the part. Hence VA should be maintained at an equal or greater voltage than VCP at all times. While "back-powering" does not have any adverse effects on device operation with respect to performance and reliability, it does lead to extra power consumption and therefore should be avoided. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current.
DS773F1
11
CS42L55 ANALOG INPUT CHARACTERISTICS
Test Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the Figure 1. "Typical Connection Diagram" on page 10; Input is a 1 kHz sine wave through the passive input filter, PGA = 0 dB; All Supplies = VA; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz. Sample Frequency = 48 kHz.
VA = 2.5 V Parameter (Note 4)
Analog In to ADC (PGA bypassed) Dynamic Range Total Harmonic Distortion + Noise A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS
VA = 1.8 V Max
-79 -26
Min
89 86 -
Typ
95 92 -85 -72 -32
Min
86 83 -
Typ
92 89 -85 -69 -29
Max
-79 -23
Unit
dB dB dB dB dB
Analog In to PGA to ADC Dynamic Range PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB Common Mode Rejection (Note 5) DC Accuracy Interchannel Gain Mismatch Gain Drift Offset Error Input Interchannel Isolation (1 kHz) HP Amp to Analog Input Isolation Full-scale Input Voltage
A-weighted unweighted A-weighted unweighted -1 dBFS -60 dBFS -1 dBFS
88 85 81 78 -
94 91 87 84 -87 -31 -83 40 0.2 100 352 90 90 83
-81 -25 -77 -
85 82 78 75 0.76*VA 0.78*VA -
91 88 84 81 -85 -28 -81 40 0.2 100 352 90 90 83 0.80*VA 0.82*VA 0.198*VA 60 40
-79 -22 -75 0.84*VA 0.86*VA -
dB dB dB dB dB dB dB dB dB ppm/C LSB dB dB dB Vpp Vpp Vpp k k
(Note 6)
RL = 10 k RL = 16
Input Impedance (Note 7)
ADC 0.76*VA PGA (0 dB) 0.78*VA PGA (+12 dB) ADC PGA
0.80*VA 0.84*VA 0.82*VA 0.86*VA 0.198*VA 60 40 -
4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table. 5. See test figure shown below. 6. SDOUT Code with HPFx=1;HPFRZx=0. 7. Measured between AINxx and AGND.
100 mVPP, 25 Hz
100
AINxA
1 F
AINxREF
Figure 2. CMRR Test Configuration 12 DS773F1
CS42L55 ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 8)
Frequency Response (20 Hz to 20 kHz) Passband Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics (48 kHz Fs) (Note 9) Passband Passband Ripple Phase Deviation Filter Settling Time (Note 10) @ 20 Hz to -3.0 dB corner to -0.05 dB corner 1.87 17.15 5.3 105/Fs 0.15 Hz Hz dB Deg s to -0.05 dB corner to -3 dB corner
Min
-0.07 0.52 33 -
Typ
0.421 0.495 7.6/Fs
Max
+0.02 -
Unit
dB Fs Fs Fs dB s
Notes: 8. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 27 to 30 on page 70) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. HPF parameters are for Fs = 48 kHz. 9. Characteristics are based on the default setting in register "HPF Control (Address 09h)" on page 47. 10. Settling time decreases at higher corner frequency settings.
DS773F1
13
CS42L55 HP OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Connections to the CS42L55 are shown in the "Typical Connection Diagram" on page 10; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 3 k, CL = 150 pF for a Line Load, and test load RL = 16 , CL = 150 pF for a headphone load. (See Figure 3 on page 15).
VA = 2.5 V Parameter (Note 11)
Line Load RL = 3 k (+2 dB Analog Gain)(Note 12) Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 92 89 1.56*VA 98 95 96 93 -84 -76 -36 -82 -74 -34 1.64*VA 90 87 -
VA = 1.8 V Max Min Typ Max Unit
Min
Typ
96 93 94 91
-
dB dB dB dB dB dB dB dB dB dB VPP
16-Bit
Full-scale Output Voltage (Note 13) HP Load RL = 16 (-4 dB Analog Gain)(Note 12) Dynamic Range 18 to 24-Bit 16-Bit A-weighted unweighted A-weighted unweighted
-78 -85 -79 -74 -30 -34 -28 -83 -72 -32 1.73*VA 1.56*VA 1.64*VA 1.73*VA
Total Harmonic Distortion + Noise Full-scale Output Voltage Output Power (Note 13) Other Characteristics for RL = 16 or 3 k Interchannel Isolation Interchannel Gain Mismatch Output Offset Voltage (Note 14) Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) 3 k 16 DAC to HPOUT (Note 14) (Note 14)
89 86 0.76*VA 16 -
95 92 93 90 -75 0.82*VA 32 90 90 0.1 0.5 100 -
88 94 85 91 92 89 -69 -75 -69 0.88*VA 0.76*VA 0.82*VA 0.88*VA 17 0.25 1.0 150 16 90 90 0.1 0.5 100 0.25 1.0 150
dB dB dB dB dB VPP mW dB dB dB mV ppm/C pF
14
DS773F1
CS42L55 LINE OUTPUT CHARACTERISTICS
Test conditions (unless otherwise specified): Connections to the CS42L55 are shown in the "Typical Connection Diagram" on page 10; Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25 C; Measurement bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 3 k, CL = 150 pF (see Figure 3 on page 15).
VA = 2.5 V Parameter (Note 11)
(+2 dB Analog Gain) (Note 12) Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
VA = 1.8 V Max Min Typ Max Unit
Min
Typ
A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB
93 90 1.50*VA 3 -
99 96 96 93 -84 -76 -36 -82 -74 -34 1.58*VA 90 0.1 0.5 100 100 -
-
91 88 -
97 94 94 91
-
dB dB dB dB dB dB dB dB dB dB VPP dB dB mV ppm/C k pF
16-Bit
Full-scale Output Voltage (Note 13) Other Characteristics Interchannel Isolation Interchannel Gain Mismatch Output Offset Voltage (Note 14) DAC to LINEOUT Gain Drift Output Impedance AC-Load Resistance (RL) Load Capacitance (CL)
-78 -86 -80 -74 -30 -34 -28 -84 -72 -32 1.66*VA 1.50*VA 1.58*VA 1.66*VA 0.25 1.0 150 3 90 0.1 0.2 100 100 0.25 1.0 150
(Note 14) (Note 14)
Notes: 11. One-half LSB of triangular PDF dither is added to data. 12. The Analog Gain setting (refer to "Headphone Volume Control" on page 57 or "Line Volume Control" on page 58) must be configured as indicated to achieve the specified output characteristics. High gain settings at certain VA and VCP supply levels may cause clipping when the audio signal approaches fullscale, maximum power output. 13. VCP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the specified THD+N performance at full-scale output voltage and power may not be achieved. 14. See Figure 3 and Figure 4 on page 15. Refer to "Parameter Definitions" on page 71.
Test Load
HPOUTx RL=16 or 3 k
LIN E O U Tx
T est Load
HPREF GND/AGND
33 0.1 F
CL=150 pF
C L =150 pF LIN E R E F G N D /A G N D
R L =3 k
+ Measurement Device
+ M easurem ent D evice
Figure 3. HP Output Test Configuration DS773F1
Figure 4. Line Output Test Configuration 15
CS42L55 ANALOG PASSTHROUGH CHARACTERISTICS
Test Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the "Typical Connection Diagram" on page 10; Input is a 1 kHz sine wave through the passive input filter shown in Figure 1, PGA and HP/Line gain = 0 dB; All Supplies = VA, VCP Mode; GND = AGND = 0 V; TA = +25 C; Measurement bandwidth is 20 Hz to 20 kHz. Sample Frequency = 48 kHz.
Parameter
Analog In to HP Amp (ADC is powered down) RL = 3 k (+2 dB Output Analog Gain)(Note 12) Dynamic Range Total Harmonic Distortion + Noise A-weighted unweighted -1 dB -20 dB -60 dB
Min
VA = 2.5 V Typ
Max
Min
VA = 1.8 V Typ
Max
Unit
Full-scale Input Voltage Full-scale Output Voltage Passband Ripple RL = 16 (-4 dB Output Analog Gain)(Note 12) Dynamic Range Total Harmonic Distortion + Noise A-weighted unweighted -1 dB -20 dB -60 dB
-
94 91 -70 -71 -31 0.80*VA 0.93*VA 0/-0.3 94 91 -70 -71 -31 0.80*VA 12 0/-0.3
-
-
91 88 -80 -68 -28 0.80*VA 0.93*VA 0/-0.3 91 88 -80 -68 -28 0.80*VA 6.5 0/-0.3
-
dB dB dB dB dB Vpp Vpp dB dB dB dB dB dB Vpp mW dB
Full-scale Input Voltage Output Power (Note 13) Passband Ripple Analog In to Line Amp (ADC is powered down) RL = 3 k (+2 dB Output Analog Gain) (Note 12) Dynamic Range Total Harmonic Distortion + Noise A-weighted unweighted -1 dB -20 dB -60 dB
-
-
-
-
Full-scale Input Voltage Full-scale Output Voltage Passband Ripple
-
94 91 -70 -71 -31 0.80*VA 0.89*VA 0/-0.3
-
-
91 88 -80 -68 -28 0.80*VA 0.89*VA 0/-0.3
-
dB dB dB dB dB Vpp Vpp dB
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 15)
Frequency Response 20 Hz to 20 kHz Passband Stopband Stopband Attenuation (Note 16) Total Group Delay De-emphasis Error Fs = 44.118 kHz Fs = 48.000 kHz Fs = 44.118 kHz to -0.05 dB corner to -3 dB corner
Min
-0.04 -0.14 0.55 49 -
Typ
0.48 0.49 9/Fs -
Max
+0.04 +0.14 +0.05/-0.25
Unit
dB dB Fs Fs Fs dB s dB
Notes: 15. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 31 to 34 on page 70) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 16. Measurement bandwidth is from Stopband to 3 Fs. 16 DS773F1
CS42L55 SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT CLOAD = 15 pF.
Parameters
RESET pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Slave Mode (Figure 5) Input Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Master Mode (Figure 6) Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Time Before SCLK Falling Edge SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge SCLK = MCLK mode All Other Modes RATIO[1:0] = `11' RATIO[1:0] = `01' (Note 18) All Speed Modes (Note 17)
Symbol
Min
1
Max
-
Units
ms MHz %
(See "Serial Port Clocking" on page 34) 45 55
Fs
(See "Serial Port Clocking" on page 34) 45 55 68*Fs 55 45 40 20 30 20 20
kHz % Hz % ns ns ns ns ns
1/tPs tss(LK-SK) tss(SDO-SK) ths(SK-SDO) tss(SD-SK) ths
Fs
(See "Serial Port Clocking" on page 34) 45 55 12.0000 68*Fs 55 66 2 45 33
Hz % MHz Hz % % ns ns ns ns ns
1/tPm 1/tPm
tsm(LK-SK) tsm(SDO-SK) thm(SK-SDO) tsm(SD-SK) thm
20 30 20 20
Notes: 17. After powering up the CS42L55, RESET should be held low after the power supplies and clocks are settled. This specification is valid with the recommended capacitor on VDFILT. 18. The device will periodically extend the SCLK high time to compensate for the fractional MCLK/SCLK ratio.
//
LRCK
tss(LK-SK) // // // tss(SDO-SK) tP // // ths(SK-SDO) // MSB // ths MSB //
//
LRCK
// // tsm(LK-SK) // // // // // tsm(SDO-SK) tPm // // thm(SK-SDO) // MSB // thm MSB //
SCLK
SCLK
SDOUT
// //
SDOUT
SDIN
//
tss(SD-SK)
SDIN
//
tsm(SD-SK)
Figure 5. Serial Port Timing (Slave Mode)
Figure 6. Serial Port Timing (Master Mode)
DS773F1
17
CS42L55 SWITCHING SPECIFICATIONS - CONTROL PORT
Inputs: Logic 0 = GND = AGND, Logic 1 = VL, SDA CL = 30 pF.
Parameter
SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 19)
Symbol
fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max
100 1 300 1000
Unit
kHz ns s s s s s s ns s ns s ns
Notes: 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RESET t irs Stop SDA t buf
SCL Repeated Start
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 7. IC Control Port Timing
18
DS773F1
CS42L55 POWER SUPPLY REJECTION (PSRR) CHARACTERISTICS
Test Conditions (unless otherwise specified): Connections to the CS42L55 are shown in the "Typical Connection Diagram" on page 10; GND = AGND = 0 V; all voltages with respect to ground.
Parameters
PSRR with 100 mVpp, 1 kHz signal (Note 20) PGA to ADC ADC PGA to HP & Line Amps DAC to HP & Line Amps PGA to ADC (Note 21) ADC PGA to HP & Line Amps DAC to HP & Line Amps
Min
-
Typ
55 50 50 50 35 25 50 60
Max
-
Units
dB dB dB dB dB dB dB dB
PSRR with 100 mVpp, 60 Hz signal (Note 20)
Notes: 20. Valid with the recommended capacitor values on FILT+ and VQ, no load on HP and Line. Increasing the capacitance on FILT+ and VQ will also increase the PSRR. 21. The PGA is biased with VQ, created by a resistor divider from the VA supply.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 22)
Input Leakage Current Input Capacitance 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 A) Low-Level Output Voltage (IOL = 100 A) High-Level Input Voltage VL = 1.65 V VL = 1.8 V VL = 2.0 V VL > 2.0 V VOH VOL VIH VL - 0.2 0.83*VL 0.76*VL 0.68*VL 0.65*VL 0.65*VA 0.2 0.30*VL 0.35*VA V V V
Symbol
Iin
Min
-
Max
10 10
Units
A pF
Low-Level Input Voltage HPDETECT Input High-Level Input Voltage Low-Level Input Voltage
VIL HPDVIH HPDVIL
V V V
22. See "I/O Pin Characteristics" on page 9 for serial and control port power rails.
1 VCP
2.2 F
Power Supply + + Voltmeter + + -
1 VA
0.1 F
1 VLDO
0.1 F
1 VL
GND/AGND
0.1 F
Note: Current is derived from the voltage drop across a 1 resistor in series with each supply input.
Figure 8. Power Consumption Test Configuration DS773F1 19
CS42L55 POWER CONSUMPTION - ALL SUPPLIES = 1.8 V
02h page 42 Operation Test Conditions (unless otherwise specified): All zeros input, slave mode, sample rate = 48 kHz; No load. Refer to Figure 8 on page 19. PDN_CHRG PDN_ADCB PDN_ADCA 1 2
Off (Note 23) Standby
03h page 43 ADCBMUX[1:0] PDN_LINB[1:0] PDN_LINA[1:0] PDN_HPB[1:0] PDN_HPA[1:0]
08h page 46 ADCAMUX[1:0]
LINEBMUX LINEAMUX HPBMUX HPAMUX PDN_DSP - 0Fh page 50
Power Ctl. Registers
ADC, Line, HP Sel. Registers
Typical Current (mA)
iVCP
iVA
iVLDO
iVL
x
MCLKDIS=1 x MCLKDIS=0 x
x x x x 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0
x x x x 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0
x 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x
x x x x
x x x x
x x x x
x x x x
x x x x
xxxxx xxxxx xxxxx xxxxx
Class H Mode page 45 0.002 0.003 0.002 0.003 0.002 0.039 0.002 0.005 0.223 0.002 0.002 0.010 0.003 0.859 0.650 0.002 1.053 0.650 0.002 1.116 0.795
Total Power (mW)
0.001 0.006 0.006 0.002 0.017 0.018 0.022 0.022 0.006 0.006 0.006 0.006 0.006 0.005 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.005 0.006 0.006 0.005 0.006 0.006 0.006 0.017 0.017 0.017 0.018 0.023 0.022 0.022 0.023 0.01 0.09 0.43 0.03 2.75 3.10 3.48 4.13 3.87 4.75 4.37 5.27 3.80 4.56 4.29 5.06 5.08 6.38 5.68 7.04 4.88 5.99 5.47 6.58 3.31 4.40 3.33 4.44 6.06 6.94 6.58 7.46 8.29 9.63 8.92 10.25
(Note 23) MCLKDIS=x x
3 4 5
Mono Record (Note 24)
ADC 0 ADC 0
PDN
11 11 11 11 xx 01 x x x x x 11 11 11 11 xx 00 x x x x x 11 11 11 11 01 01 x x x x x 11 11 11 11 00 00 x x x x x 11 10 11 11 xx xx x x x 0 1 11 10 11 11 xx xx x x x 0 0 11 11 11 10 xx xx x 0 x x 1 11 11 11 10 xx xx x 0 x x 0 10 10 11 11 xx xx x x 0 0 1 10 10 11 11 xx xx x x 0 0 0 11 11 10 10 xx xx 0 0 x x 1 11 11 10 10 xx xx 0 0 x x 0 10 10 11 11 xx xx x x 1 1 x 11 11 10 10 xx xx 1 1 x x x 11 10 11 11 xx 00 x x x 0 1 11 10 11 11 xx 00 x x x 0 0 10 10 11 11 00 00 x x 0 0 1 10 10 11 11 00 00 x x 0 0 0
PGA to ADC 0 Stereo Record (Note 24) PGA to ADC 0 Mono Play to HP No Effects 1 Effects 1
0.002 1.470 0.800 VCP/2 0.450 1.007 0.686 VCP 0.928 1.014 0.690 VCP/2 0.452 1.008 0.964 VCP 0.936 1.014 0.972 VCP/2 0.394 1.008 0.704 VCP 0.822 1.015 0.692 VCP/2 0.394 1.008 0.977 VCP 0.822 1.015 0.969 VCP/2 0.697 1.434 0.688 VCP 1.405 1.441 0.692 VCP/2 0.693 1.435 1.023 VCP 1.429 1.442 1.031 VCP/2 0.572 1.437 0.697 VCP 1.182 1.443 0.698 VCP/2 0.572 1.437 1.025 VCP 1.182 1.445 1.025 VCP/2 0.562 1.083 0.190 VCP 1.159 1.090 0.190 VCP/2 0.572 1.084 0.190 VCP 1.181 1.093 0.190 VCP/2 0.450 1.838 1.063 VCP 0.931 1.846 1.061 VCP/2 0.453 1.839 1.346 VCP 0.937 1.846 1.345 VCP/2 0.689 2.682 1.209 VCP 1.417 2.690 1.218 VCP/2 0.693 2.682 1.560 VCP 1.420 2.691 1.561
6
Mono Play to Line
No Effects 1 Effects 1
7
Stereo Play to HP
No Effects 1 Effects 1
8
Stereo Play to Line
No Effects 1 Effects 1
9
Stereo Passthrough to HP
0 0
10 Stereo Passthrough to Line 11 Mono Rec. & Play
PGA In, HP Out
No Effects 0 Effects 0
12 Stereo Rec. & Play
PGA In, HP Out
No Effects 0 Effects 0
20
DS773F1
CS42L55 POWER CONSUMPTION - ALL SUPPLIES = 2.5 V
02h page 42 LINEBMUX LINEAMUX HPBMUX HPAMUX PDN_DSP - 0Fh page 50
Power Ctl. Registers Operation Test Conditions (unless otherwise specified): /All zeros input, slave mode, sample rate = 48 kHz; No load. Refer to Figure 8 on page 19.
1 2
Off (Note 23) Standby
MUX Registers
08h page 46 ADCBMUX[1:0] ADCAMUX[1:0]
Typical Current (mA)
iVCP iVA iVLDO iVL
03hpage 43 PDN_LINB[1:0] PDN_LINA[1:0] PDN_HPB[1:0] PDN_HPA[1:0]
PDN_CHRG
PDN_ADCB
PDN_ADCA
x
MCLKDIS=1 x MCLKDIS=0 x
x x x x 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0
x x x x 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0
x 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
x x x x
x x x x
x x x x
x x x x
x x x x
x x x x
xxxxx xxxxx xxxxx xxxxx
Class H Mode page 45 0.001 0.001 0.001 0.000 0.000 0.000 0.064 0.007 0.000 0.013 0.385 0.007 0.000 0.000 0.018 0.000 0.000 0.752 0.743 0.019 0.000 0.997 0.750 0.019 0.000 1.031 0.918 0.025
Total Power (mW)
0.01 0.18 1.01 0.05 3.79 4.42 4.94 6.15 6.79 9.37 7.60 10.30 6.65 9.00 7.36 9.73 8.74 12.13 9.69 13.03 8.33 11.21 9.22 12.01 5.36 8.22 5.38 8.23 9.77 12.46 10.53 13.11 13.45 16.81 14.38 17.68
(Note 23) MCLKDIS=x x
3 4 5
Mono Record (Note 24)
ADC 1 ADC 1
PDN
11 11 11 11 xx 01 x x x x x 11 11 11 11 xx 00 x x x x x 11 11 11 11 01 01 x x x x x 11 11 11 11 00 00 x x x x x 11 10 11 11 xx xx x x x 0 1 11 10 11 11 xx xx x x x 0 0 11 11 11 10 xx xx x 0 x x 1 11 11 11 10 xx xx x 0 x x 0 10 10 11 11 xx xx x x 0 0 1 10 10 11 11 xx xx x x 0 0 0 11 11 10 10 xx xx 0 0 x x 1 11 11 10 10 xx xx 0 0 x x 0 10 10 11 11 xx xx x x 1 1 x 11 11 10 10 xx xx 1 1 x x x 11 10 11 11 xx 00 x x x 0 1 11 10 11 11 xx 00 x x x 0 0 10 10 11 11 00 00 x x 0 0 1 10 10 11 11 00 00 x x 0 0 0
PGA to ADC 1 Stereo Record (Note 24) PGA to ADC 1 Mono Play to HP No Effects 1 Effects 1
0.000 1.511 0.926 0.024 VCP/2 0.676 1.327 0.705 0.007 VCP 1.694 1.339 0.709 0.007 VCP/2 0.677 1.325 1.032 0.007 VCP 1.728 1.337 1.049 0.007 VCP/2 0.585 1.328 0.738 0.007 VCP 1.516 1.339 0.739 0.007 VCP/2 0.585 1.324 1.030 0.006 VCP 1.515 1.338 1.030 0.007 VCP/2 0.943 1.833 0.711 0.007 VCP 2.250 1.850 0.744 0.007 VCP/2 0.945 1.835 1.090 0.007 VCP 2.237 1.846 1.121 0.007 VCP/2 0.760 1.835 0.730 0.007 VCP 1.888 1.848 0.740 0.006 VCP/2 0.760 1.836 1.085 0.007 VCP 1.888 1.851 1.058 0.007 VCP/2 0.751 1.174 0.212 0.007 VCP 1.880 1.188 0.212 0.007 VCP/2 0.759 1.175 0.211 0.007 VCP 1.886 1.189 0.211 0.007 VCP/2 0.676 2.055 1.159 0.018 VCP 1.700 2.068 1.196 0.018 VCP/2 0.678 2.055 1.462 0.018 VCP 1.696 2.066 1.463 0.018 VCP/2 0.945 3.071 1.340 0.024 VCP 2.254 3.089 1.358 0.023 VCP/2 0.950 3.074 1.702 0.024 VCP 2.254 3.090 1.705 0.023
6
Mono Play to Line
No Effects 1 Effects 1
7
Stereo Play to HP
No Effects 1 Effects 1
8
Stereo Play to Line
No Effects 1 Effects 1
9
Stereo Passthrough to HP
1 1
10 Stereo Passthrough to Line 11 Mono Rec. & Play
PGA In, HP Out
No Effects 1 Effects 1
12 Stereo Rec. & Play
PGA In, HP Out
No Effects 1 Effects 1
Notes: 23. When "Off", RESET pin and clock/data lines held LO; when in "standby", lines are held HI. 24. Either inputs 1 or 2 may be selected. Input 1 is shown for simplicity.
DS773F1
21
CS42L55 4. APPLICATIONS
4.1 4.1.1 Overview Basic Architecture
The CS42L55 is a highly integrated, ultra-low power, 24-bit audio CODEC comprised of stereo A/D and D/A converters with pseudo-differential stereo input and output amplifiers. The ADC and DAC are designed using multi-bit delta-sigma techniques; both converters operate at a low oversampling ratio of 64xFs, maximizing power savings while maintaining high performance. The CODEC operates in one of three sample rate speed modes: Quarter, Half and Single. It accepts and is capable of generating serial audio clocks (SCLK, LRCK) derived from a 12 or 6 MHz input Master Clock (MCLK). Designed with a very low voltage digital core and low voltage Class H amplifiers (powered from an integrated low-dropout regulator and a step-down/inverting charge pump, respectively), the CS42L55 provides significant reduction in overall power consumption.
4.1.2
Line Inputs
The analog input portion of the CODEC allows selection from two stereo line-level sources into a Programmable Gain Amplifier (PGA). The optional pseudo-differential configuration provides noise-rejection for single-ended inputs.
4.1.3
Line and Headphone Outputs (Class H, Ground-Centered Amplifiers)
The analog output portion of the CODEC includes separate pseudo-differential headphone and line out Class H amplifiers. An on-chip step-down/inverting charge pump creates a positive and negative voltage equal to the input or one-half the input supply for the amplifiers, allowing an adaptable, full-scale output swing centered around ground. The inverting architecture eliminates the need for large DC-blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. The step-down architecture allows the amplifier's power supply to adapt to the required output signal. This adaptive power supply scheme converts traditional Class AB amplifiers into more power-efficient Class H amplifiers.
4.1.4
Fixed-Function DSP Engine
The fixed function digital signal processing engine processes both the PCM serial input data and ADC output data allowing a mix between the two. Independent volume control, left/right channel swaps, mono mixes, tone control comprise the DSP engine.
4.1.5
Beep Generator
The beep generator delivers tones at select frequencies across approximately two octave major scales. With independent volume control, beeps may be configured to occur continuously, periodically or at single time intervals.
4.1.6
Power Management
Several control registers and bits provide independent power down control of the ADC, PGA, DSP, headphone and line outputs, allowing operation in select applications with minimal power consumption.
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4.2 Analog Inputs
BOOSTA ADCAMUTE DIGSFT ADCAATT[7:0] ADCB=A HPFRZA HPFA HPFA_CF[1:0] PDN_ADCA INV_ADCA PDN_CHRG
AIN1A
AIN2A Gain Adjust
ADC
ADCAMUX[1:0] DIGSUM[1:0] ALCA ALCASRDIS ALCAZCDIS ALCARATE[5:0] ALCRRATE[5:0] MAX[2:0] MIN[2:0] ALCB ALCBSRDIS ALCBZCDIS ADCBMUX[1:0]
PGAAMUX PDN_ADCA PGAAVOL[5:0] PGAB=A ANLGZC
PCM Serial Interface
AIN1REF
Swap/ Mix
DIGMUX
ALC
Noise Gate
NGALL NG THRESH[3:0] NGDELAY[1:0]
PDN_ADCB PGABVOL[5:0] PGAB=A ANLGZC PGABMUX
AIN2REF
Gain Adjust
ADC
BOOSTB ADCBMUTE DIGSFT ADCBATT[7:0] ADCB=A
AIN2B
HPFRZB HPB HPFB_CF[1:0] PDN_ADCB INV_ADCB PDN_CHRG
AIN1B
TO DSP Engine
ANALOG PASSTHRU TO HEADPHONE, LINE AMPLIFIER MUX
FROM DSP ENGINE
Figure 9. Analog Input Signal Flow
Referenced Control
Analog Front End PGAxMUX PDN_ADCx PGAxVOL[5:0] PGAB=A ANLGZCx ADCxMUX[1:0] INV_ADCx PDN_CHRG HPFRZx HPFx HPFx_CF[1:0] Digital Volume BOOSTx ADCxMUTE ADCxATT[7:0] DIGSFT ADCB=A ALCx ALCxSRDIS ALCxZCDIS ALCARATE[5:0] ALCRRATE[5:0] MAX[2:0] MIN[2:0] NGALL NG THRESH[3:0] NGDELAY[1:0] Miscellaneous DIGSUM[1:0] DIGMUX
Register Location
"PGA x Input Select" on page 49 "Power Down ADC x" on page 42 "PGAx Volume" on page 49 "PGA Channel B=A" on page 48 "Analog Zero Cross" on page 46 "ADC x Input Select" on page 46 "Invert ADC Signal Polarity" on page 48 "Power Down ADC Charge Pump" on page 42 "ADCx High-Pass Filter Freeze" on page 47 "ADCx High-Pass Filter" on page 47 "HPF x Corner Frequency" on page 47 "Boostx" on page 49 "ADC Mute" on page 48 "ADCx Volume" on page 50 "Digital Soft Ramp" on page 46 "ADC Channel B=A" on page 48 "ALCx" on page 62 "ALCx Soft Ramp Disable" on page 65 "ALCx Zero Cross Disable" on page 65 "ALC Attack Rate" on page 63 "ALC Release Rate" on page 63 "ALC Maximum Threshold" on page 64 "ALC Minimum Threshold" on page 64 "Noise Gate All Channels" on page 64 "Noise Gate Enable" on page 65 "Noise Gate Threshold and Boost" on page 65 "Noise Gate Delay Timing" on page 65 "Digital Sum" on page 48 "Digital MUX" on page 45
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4.2.1 Pseudo-Differential Inputs
The CS42L55 implements a pseudo-differential input stage. The AINxREF inputs are intended to be used as a pseudo-differential reference signal. This feature provides 0 noise rejection with single-ended signals. Figure 10 shows a basic diagram outlining the internal implementation of the pseudo-differential input stage, including a recommended stereo pseudo-differential input topology. If pseudo-differential input functionality is not required, simply leave the AINxREF pin floating.
PGAAMUX='0'b
1 F
Left Input
// //
1 F
AIN1A
26
+ PGA A
(differential traces)
AIN1REF
27
GND
common mode rejection at input of PGA reduces external system noise
1 F
Right Input
// //
1 F
AIN2B
25
+ PGA B
(differential traces)
AIN2REF
24
GND
-
PGABMUX='1'b
Figure 10. Stereo Pseudo-Differential Input Referenced Control Register Location
PGAxMUX ........................... "PGA x Input Select" on page 49
4.2.2
Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator. The ALC then detects when peak levels exceed the maximum threshold settings and first lowers the PGA gain settings and then increases the digital attenuation levels at a programmable attack rate and maintains the resulting level below the maximum threshold. When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first and the PGA gain is then increased at a programmable release rate and maintains the resulting level above the minimum threshold. Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC soft ramp and zero cross dependency may be independently enabled/disabled. Recommended settings: Best level control may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. Notes: 1. When ALC x is enabled and the PGAxVOL[5:0] is set to +12 dB, the ADCxATT[7:0] should not be set below 0 dB. 2. The maximum desired gain must be set in the PGAxVOL register. The ALC will only apply the gain set in PGAxVOL. 3. The ALC maintains the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-controlled output may not always be the same but will always fall between the thresholds.
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Referenced Control Register Location
PGAxVOL[5:0] ..................... "PGAx Volume" on page 49 ADCxATT[7:0] ...................... "ADCx Volume" on page 50 MAX[2:0], MIN[2:0] .............. "ALC Threshold (Address 26h)" on page 64
Input (before ALC) MIN[2:0]
below full scale
MAX[2:0]
below full scale
ALC Response
PGA Gain and/or Attenuator
Output (after ALC) MIN[2:0]
below full scale
MAX[2:0]
below full scale
RRATE[5:0]
ARATE[5:0 ]
Figure 11. ALC Operation
4.3
Analog In to Analog Out Passthrough
The CS42L55 accommodates analog routing of the analog input signal directly to the headphone and line out amplifiers. This feature is useful in applications that utilize an FM tuner where audio recovered over-theair must be transmitted to the headphone amplifier without digital conversion in the ADC and DAC. This analog passthrough path reduces power consumption and is immune to modulator switching noise that could interfere with some tuners. This path is selected using the Line and/or HP mux bits and powering down the ADC.
Referenced Control Register Location
PDN_ADCx ......................... "Power Down ADC x" on page 42 HPxMUX.............................. "Headphone Input Select" on page 47 LINExMUX........................... "Line Input Select" on page 47
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4.4 Analog Outputs
INPUTS FROM ADCA and ADCB
Fixed Function DSP
AMIXAMUTE AMIXBMUTE AMIXAVOL[6:0] AMIXBVOL[6:0] MSTAVOL[7:0] MSTBVOL[7:0]
LIMARATE[7:0] LIMRRATE[7:0] LMAX[2:0] CUSH[2:0] LIMSRDIS LIMIT LIMIT_ALL
VOL
PMIXAMUTE PMIXBMUTE PMIXAVOL[6:0] PMIXBVOL[6:0] PCMASWAP[1:0] PCMBSWAP[1:0]
Chnl Vol. Settings
Channel Swap
Limiter
PCM Serial Interface
ADCASWAP[1:0] ADCBSWAP[1:0]
Peak Detect
Demph
DEEMPH
VOL
Channel Swap
VOL
VOL
Bass/ Treble/ Control
TC_EN BASS_CF[1:0] TREB_CF[1:0] BASS[3:0] TREB[3:0] PDN_DSP
DAC
to HP and Line MUX
INV_PCMA INV_PCMB BPVOL[4:0] MSTAMUTE MSTBMUTE DIGSFT PLYBCKB=A
OFFTIME[2:0] ONTIME[3:0] FREQ[3:0] BEEP[1:0]
Beep Generator
*
Digital Mix to ADC Serial Interface
*
MSTxVOL[7:0], MSTxMUTE and DIGSFT are always available regardless of the PDN_DSP setting.
Figure 12. DSP Engine Signal Flow
Referenced Control
DSP PDN_DSP DEEMPH PMIXxMUTE PMIXxVOL[6:0] INV_PCMx PCMxSWAP[1:0] AMIXxMUTE AMIXxVOL[6:0] ADCxSWAP[1:0] MSTxVOL[7:0] MSTxMUTE DIGSFT PLYBCKB=A TC_EN BASS_CF[1:0] TREB_CF[1:0] BASS[3:0] TREB[3:0] Limiter LIMIT LIMIT_ALL LIMSRDIS LMAX[2:0] CUSH[2:0] LIMARATE[7:0] LIMRRATE[7:0] Beep Generator
Register Location
"Power Down DSP" on page 50 "HP/Line De-Emphasis" on page 50 "PCM Mixer Channel x Mute" on page 52 "PCM Mixer Channel x Volume" on page 52 "Invert PCM Signal Polarity" on page 51 "PCM Mix Channel Swap" on page 60 "ADC Mixer Channel x Mute" on page 51 "ADC Mixer Channel x Volume" on page 51 "ADC Mix Channel Swap" on page 60 "Master Volume Control" on page 57 "Master Playback Mute" on page 51 "Digital Soft Ramp" on page 46 "Playback Channels B=A" on page 50 "Tone Control Enable" on page 56 "Bass Corner Frequency" on page 56 "Treble Corner Frequency" on page 55 "Bass Gain" on page 56 "Treble Gain" on page 56 "Peak Detect and Limiter" on page 61 "Peak Signal Limit All Channels" on page 61 "Limiter Soft Ramp Disable" on page 66 "Limiter Maximum Threshold" on page 60 "Limiter Cushion Threshold" on page 61 "Limiter Attack Rate" on page 62 "Limiter Release Rate" on page 62 Refer to "Beep Generator" on page 31 for all referenced controls
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ADPTPWR[1:0] Step-down/Inverting Charge Pump Class H Control +VCP +VCP/2 -VCP -VCP/2 CHGFREQ[3:0]
+HP Supply +Line Supply
= HP and Line Supply HP Detection PDN_HPx[1:0] PDN_LINx[1:0]
VCP
HPDETECT
+VHPFILT
from PGAx from DACx
HPxMUX
HPxVOL[6:0] HPxMUTE ANLGZC PLYBCKB=A
HPOUTA HPOUTB HPREF
LINExMUX
LINEOUTA LINEOUTB LINEREF
LINExVOL[6:0] LINExMUTE ANLGZC PLYBCKB=A
-HP Supply -Line Supply
-VHPFILT
Figure 13. Analog Output Stage
Referenced Control
Analog Output ADPTPWR[1:0] CHGFREQ[3:0] PDN_HPx[1:0] PDN_LINx[1:0] HPxMUTE HPxVOL[7:0] LINExMUTE LINExVOL[7:0] ANLGZC PLYBCKB=A HPxMUX LINExMUX
Register Location
"Adaptive Power Adjustment" on page 45 "Charge Pump Frequency" on page 67 "Headphone Power Control" on page 43 "Line Power Control" on page 43 "Headphone Channel x Mute" on page 57 "Headphone Volume Control" on page 57 "Line Channel x Mute" on page 58 "Line Volume Control" on page 58 "Analog Zero Cross" on page 46 "Playback Channels B=A" on page 50 "Headphone Input Select" on page 47 "Line Input Select" on page 47
4.5
Class H Amplifier
The CS42L55 headphone and line output amplifiers use a patented Cirrus Logic Bi-Modal Class H technology. This technology maximizes operating efficiency of the typical Class AB amplifier while maintaining high performance. In a Class H amplifier design, the rail voltages supplied to the amplifier vary with the needs of the music passage that is being amplified. This prevents unnecessarily wasting energy during low power passages of program material or when the program material is played back at a low volume level. The central component of the Bi-Modal Class H technology found in the CS42L55 is the internal charge pump, which creates the rail voltages for the headphone and line amplifiers of the device. The charge pump receives its input voltage from the voltage present on the VCP pin of the CS42L55. From this input voltage, the charge pump creates the differential rail voltages that are supplied to the amplifier output stages. The charge pump is capable of supplying two sets of differential rail voltages. One set is equal to VCP and the other is equal to VCP/2.
4.5.1
Power Control Options
The method by which the CS42L55 decides which set of rail voltages is supplied to the amplifier output stages depends on the settings of the Adaptive Power bits (ADPTPWR) found in "Class H Power Control (Address 06h)" section on page 45. As detailed in this section, there are four possible settings for these bits: Mode 00, 01, 10 and 11.
Referenced Control Register Location
ADPTPWR[1:0] ................... "Adaptive Power Adjustment" on page 45
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CS42L55
4.5.1.1 Standard Class AB Operation (Mode 01 and 10)
When the Adaptive Power bits are set to either 01 or 10, the rail voltages supplied to the amplifiers will be held to VCP/2 or VCP, respectively. For these two settings, the rail voltages supplied to the output stages are held constant, regardless of the signal level, internal volume settings, or the settings of the AIN and DIN advisory volume registers. In either of these two settings, the amplifiers in the CS42L55 simply operate in a traditional Class AB configuration.
4.5.1.2
Adapted to Volume Settings (Mode 00)
When the Adaptive Power bits are set to 00, the CS42L55 decides which set of rail voltages to send to the amplifiers based upon the gain and attenuation levels of all active internal processing blocks. In order to adjust for external analog (line or microphone sources) or digital (DSP) input volume settings, it also takes into account the settings of the AIN and DIN advisory volume registers. The combined effect of all volume settings is shown in Figure 14.
Analog Input Source
IS Serial Audio Input Control Port Headphone Amplifier External DSP PMIX, AMIX Volume Setting AIN Advisory Volume Setting Control Logic Master Volume Setting Headphone or Line Volume Setting Line Amplifier Charge Pump DIN Advisory Volume Setting
Figure 14. Adaptive Mode 00 If the total gain and attenuation set in the volume control registers would cause the amplifiers to clip a fullscale signal when operating from the lower set of rail voltages, the control logic instructs the charge pump to provide the higher set of the two rail voltages (VCP) to the amplifiers. If the total gain and attenuation set in the volume control registers would not cause the amplifiers to clip a full-scale signal when operating from the lower set of rail voltages, the control logic instructs the charge pump to supply the lower set of rail voltages (VCP/2) to the amplifiers. Note: The A and B channels of each respective volume control must both cross the threshold to trigger a change in the VCP mode. The control logic also monitors various functions (listed in the table below) that may affect the total gain and attenuation of the signal applied to the amplifiers.
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Referenced Control
HPxVOL[7:0] ....................... LINExVOL[7:0] .................... MSTxVOL[7:0]..................... MSTxMUTE......................... AMIXxVOL[6:0].................... PMIXxVOL[6:0].................... AINADV[7:0] ........................ DINADV[7:0]........................ BOOSTx .............................. ADCxMUX ........................... PGAxVOL............................ ADCxMUTE......................... ADCxSWP........................... PCMxSWP .......................... HPxMUX.............................. LINExMUX........................... HPxMUTE ........................... LINExMUTE ........................ PDN_HPx ............................ PDN_LINEx ......................... TREB................................... BASS................................... TCEN................................... BEEP................................... BPVOL ................................ ADCB=A .............................. PGAB=A .............................. PLYBCKB=A........................
Register Location
"Headphone Volume Control" on page 57 "Line Volume Control" on page 58 "Master Volume Control" on page 57 "Master Playback Mute" on page 51 "ADC Mixer Channel x Volume" on page 51 "PCM Mixer Channel x Volume" on page 52 "Analog Input Advisory Volume" on page 59 "Digital Input Advisory Volume" on page 59 "Boostx" on page 49 "ADC x Input Select" on page 46 "PGAx Volume" on page 49 "ADC Mute" on page 48 "ADC Mix Channel Swap" on page 60 "PCM Mix Channel Swap" on page 60 "Headphone Input Select" on page 47 "Line Input Select" on page 47 "Headphone Channel x Mute" on page 57 "Line Channel x Mute" on page 58 "Headphone Power Control" on page 43 "Line Power Control" on page 43 "Treble Gain" on page 56 "Bass Gain" on page 56 "Tone Control Enable" on page 56 "Beep Configuration" on page 55 "Beep Volume" on page 55 "ADC Channel B=A" on page 48 "PGA Channel B=A" on page 48 "Playback Channels B=A" on page 50
4.5.1.3
Adapted to Output Signal (Mode 11)
When the Adaptive Power bits are set to 11, the CS42L55 decides which of the two sets of rail voltages to send to the amplifiers based solely upon the level of the signal being sent to the amplifiers. If the signal that is sent to the amplifiers would cause the amplifiers to clip when operating on the lower set of rail voltages, the control logic instructs the charge pump to provide the higher set of rail voltages (VCP) to the amplifiers. If the signal that is sent to the amplifiers would not cause the amplifiers to clip when operating on the lower set of rail voltages, the control logic instructs the charge pump to provide the lower set of rail voltages (VCP/2) to the amplifiers. This mode of operation eliminates the need to advise the CS42L55 of volume settings external to the device. Note: Signal detection is made using digital circuitry. This mode should, therefore, not be used with analog passthrough (PGA to HP/Line).
4.5.2
Power Supply Transitions
Charge pump transitions from the lower set of rail voltages to the higher set of rail voltages occur on the next FLYN/P clock cycle. Despite the fast response time of the system, the capacitive elements on the VHPFILT pins prevent the rail voltages from changing instantaneously. Instead, the rail voltages ramp up from VCP/2 to VCP based on the time constant created by the output impedance of the charge pump and the capacitor on the VHPFILT pin (the transition time is approximately 20 s). This behavior is detailed in Figure 15. During this charging transition, a high dv/dt transient on the inputs may briefly clip the outputs before the rail voltages charge to the full VCP level. This transitory clipping has been found to be inaudible in listening tests.
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Ideal Transition +VCP
+VCP 2 Actual Transition caused by VHPFILT Capacitor
Time
Actual Transition caused by VHPFILT Capacitor -VCP 2
-VCP Ideal Transition
Figure 15. VHPFILT Transitions When the charge pump transitions from the higher set of rail voltages to the lower set, there is a one second delay before the charge pump supplies the lower rail voltages to the amplifiers. This hysteresis ensures that the charge pump doesn't toggle between the two rail voltages as signals approach the clip threshold. It also prevents clipping in the instance of repetitive high level transients in the input signal. The timing diagram for this transitional behavior is detailed in Figure 16.
Output Level 1 second
-10 dB Time
Amplifier Rail Voltage
VCP VCP 2 Time - VCP 2 - VCP
Figure 16. VHPFILT Hysteresis
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4.5.3 Efficiency
As discussed in previous sections, the amplifiers internal to the CS42L55 operate from one of two sets of rail voltages, based upon the needs of the signal being amplified or the total gain/attenuation settings. The power curves for the two modes of operation are shown in Figure 15. This graph details the power supplied to a load versus the power drawn from the supply for each of the three use cases. All Supplies= 1.8 V RL = 32
VCP Class AB Amplifiers do not conserve power with typical headphone loads. Class H Amplifiers automatically switch between VCP and VCP/2 to conserve power with typical headphone loads. VCP/2
Figure 17. Class H Power to Load vs. Power from VCP Supply When the rail voltages are set to VCP, the amplifiers will operate in their least efficient mode. When the rail voltages are held at VCP/2, the amplifiers will operate in their most efficient mode, but will be will clipped if required to amplify a full-scale signal. Note: The VCP/2 curve ends at the point at which the output of the amplifiers reached 10% THD+N.
The benefit of Bi-Modal Class H is shown in the solid trace on the graph. At lower output levels, the amplifiers operate on the VCP/2 curve. At higher output levels, they operate on the VCP curve. The duration the amplifiers will operate on either of the two curves (VCP/2 or VCP) depends on both the content and the output level of the program material being amplified. The highest efficiency operation will result from maintaining an output level that is close to, but not exceeding, the clip threshold of the VCP/2 curve.
4.6
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen On and eight Off times are available. Note: The Beep is generated before the limiter and may affect desired limiting performance. If the limiter function is used, it may be necessary to set the beep volume sufficiently below the threshold to prevent the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep volume, the DAC volume may alternatively be controlled using the PMIXxVOL[6:0] bits.
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BEEP[1:0] = '11' CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on until REPEAT is cleared.
BEEP[1:0] = '10'
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME and turns off for the duration of OFFTIME. On and off cycles are repeated until REPEAT is cleared. SINGLE-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME. BEEP must be cleared and set for additional beeps.
BEEP[1:0] = '01'
BPVOL[4:0]
...
FREQ[3:0] ONTIME[3:0] OFFTIME[2:0]
Figure 18. Beep Configuration Options
Referenced Control
MSTxVOL[7:0]..................... PMIXxVOL[6:0].................... OFFTIME[2:0]...................... ONTIME[3:0] ....................... FREQ[3:0] ........................... BEEP[1:0]............................ BPVOL[4:0] .........................
Register Location
"Master Volume Control: MSTA (Address 18h) & MSTB (Address 19h)" on page 57 "PCMx Mixer Volume: PCMA (Address 12h) & PCMB (Address 13h)" on page 52 "Beep Off Time" on page 54 "Beep On Time" on page 54 "Beep Frequency" on page 53 "Beep Configuration" on page 55 "Beep Volume" on page 55
4.7
Limiter
When enabled, the limiter monitors the digital input signal before the DAC modulators, detects when levels exceed the maximum threshold settings and lowers the master volume at a programmable attack rate below the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT volume returns to its original level set in the Master Volume Control register at a programmable release rate. Attack and release rates are affected by the DAC soft ramp settings and sample rate, Fs. Limiter soft ramp dependency may be independently enabled/disabled using the LIMSRDIS. Notes: 1. Recommended settings: Best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. The CUSH bits allow the user to set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases. 2. The Limiter maintains the output signal between the CUSH and MAX thresholds. As the digital input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds.
Referenced Control
Limiter Rates ....................... Limiter Thresholds LIMSRDIS ........................... Master Volume Control........
Register Location
"Limiter Release Rate" on page 62, "Limiter Attack Rate" on page 62 "Limiter Maximum Threshold" on page 60, "Limiter Cushion Threshold" on page 61 "Limiter Soft Ramp Disable" on page 66 "Master Volume Control: MSTA (Address 18h) & MSTB (Address 19h)" on page 57
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Input
MAX[2:0]
Limiter
ATTACK/RELEASE SOUND CUSHION
Volume
Output (after Limiter) CUSH[2:0]
MAX[2:0]
ARATE[5:0]
RRATE[5:0]
Figure 19. Peak Detect & Limiter
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4.8 Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated clocks in Slave Mode (M/S = `0'b) and will generate synchronous clocks derived from an input master clock (MCLK) in Master Mode (M/S = `1'b). Refer to the table below for the required setting in register 05h associated with a given MCLK and sample rate.
Referenced Control Register Location Register 05h ........................ "Clocking Control 2 (Address 05h)" on page 44 M/S ...................................... "Master/Slave Mode" on page 43
MCLK (MHz)
12.0000
(MCLKDIV2='1'b)
6.0000
(MCLKDIV2='0'b)
LRCK (kHz) Clock Ratio SPEED[1:0] 32kGROUP RATIO[1:0] Register 05h 8.0000 1500 11 1 01 0x1D 11.0294 1088 11 0 11 0x1B 12.0000 1000 11 0 01 0x19 16.0000 750 10 1 01 0x15 22.0588 544 10 0 11 0x13 24.0000 500 10 0 01 0x11 32.0000 375 01 1 01 0x0D 44.1180 272 01 0 11 0x0B 48.0000 250 01 0 01 0x09 8.0000 750 11 1 01 0x1D 11.0294 544 11 0 11 0x1B 12.0000 500 11 0 01 0x19 16.0000 375 10 1 01 0x15 22.0588 272 10 0 11 0x13 24.0000 250 10 0 01 0x11 32.0000 187.5 01 1 01 0x0D 44.1180 136 01 0 11 0x0B 48.0000 125 01 0 01 0x09
4.9
Digital Interface Format
The serial port operates in the IS digital interface formats with varying bit depths up to 24 into the DAC and a fixed depth of 24 out the ADC. Data is clocked out of the ADC on an internally delayed version of the rising SCLK edge. This provides more setup time for capturing data on the rising edge of SCLK. Data is clocked into the DAC on the rising edge of SCLK.
LRCK SCLK SDIN SDOUT
M SB
L eft C h a n n el
R ig ht C h a n n el
LS B AOUTA / AINxA
MSB AOUTB / AINxB
LSB
MSB
Figure 20. IS Format
4.10
Initialization
The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The charge pump, LDO, internal voltage reference and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions in the "Register Description" on page 42.
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After the PDN bit is released and MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. MCLK occurrences are counted over one LRCK period to determine a valid MCLK/LRCK ratio and normal operation begins.
4.11
Recommended DAC to HP or Line Power-Up Sequence (Playback)
1. Hold RESET low until the power supplies are stable; no specific power supply sequencing is required. RESET should be held low for a minimum of 1 ms after power supplies are stable. 2. Apply MCLK (LRCK, SCLK and SDIN may be applied at any time) at the appropriate frequency. 3. Bring RESET high. 4. Wait a minimum of 500 ns before writing to the control port. 5. The default state of the master power down bit, PDN, is `1'b. Load the following register settings while keeping the PDN bit set to `1'b. 6. Load the required register settings detailed in 4.13 "Required Initialization Settings" on page 37. 7. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation. Register Controls: PDN_HPx[1:0], PDN_LINx[1:0] 8. Configure the serial port I/O control for master or slave operation. Register Controls: M/S 9. Configure the master clock (MCLK) and bit clock (SCLK) I/O control as desired. Refer to 4.8 "Serial Port Clocking" on page 34 for the required configuration for a given master clock. Register Controls: MCLKDIV2, SCK=MCK 10. Configure the sample rate (LRCK) controls for the desired sample rate. Refer to 4.8 "Serial Port Clocking" on page 34 for the required configuration for a given sample rate. Register Controls: See Register 05h 11. The default state of the DSP engine's power down bit, PDN_DSP, is `0'b. It is not necessary to power down the DSP before changing the various DSP functions. The DSP may be powered down for additional power savings. 12. To minimize pops on the headphone or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0] 13. After muting the headphone or line amplifiers, set the PDN bit to `0'b. 14. Wait 75 ms for the headphone or line amplifier to power up. 15. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level. 16. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
Power Up Sequence Step 5, 13 ............................ Step 7 .................................. Steps 8-9 ............................. Step 10 ................................ Step 11 ................................ Step 12a,15a ....................... Step 12b,15b ....................... Register Location "Power Down" on page 42 "Power Control 2 (Address 03h)" on page 43 "Clocking Control 1 (Address 04h)" on page 43 "Clocking Control 2 (Address 05h)" on page 44 "Power Down DSP" on page 50 "Headphone Channel x Mute" on page 57, "Line Channel x Mute" on page 58 "Headphone Volume Control" on page 57, "Line Volume Control" on page 58
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4.11.1 Recommended Power-Down Sequence
1. To minimize pops on the headphone or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0] 2. Set the PDN bit to `1'b. 3. Bring RESET low.
Power Down Sequence Register Location Step 1a ................................ "Headphone Volume Control" on page 57, "Line Volume Control" on page 58 Step 1b ................................ "Headphone Channel x Mute" on page 57, "Line Channel x Mute" on page 58 Step 2 .................................. "Power Down" on page 42
4.12
Recommended PGA to HP or Line Power-Up Sequence (Analog Passthrough)
1. Hold RESET low until the power supplies are stable; no specific power supply sequencing is required. RESET should be held low for a minimum of 1 ms after power supplies are stable. 2. Apply MCLK at the appropriate frequency. 3. Bring RESET high. 4. Wait a minimum of 500 ns before writing to the control port. 5. The default state of the master power down bit, PDN, is `1'b. Load the following register settings while keeping the PDN bit set to `1'b. 6. Load the required register settings detailed in 4.13 "Required Initialization Settings" on page 37. 7. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation. Register Controls: PDN_HPx[1:0], PDN_LINx[1:0] 8. Configure the HP and/or Line amplifiers to receive the analog output from the PGA. Register Controls: LINExMUX, HPxMUX 9. Power down the DSP engine. Register Controls: PDN_DSP 10. To minimize pops on the headphone or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0] 11. After muting the headphone and/or line amplifiers, set the PDN bit to `0'b. 12. Wait 75 ms for the headphone or line amplifier to power up. 13. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level. 14. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
Power Up Sequence Step 5, 11 ............................ Step 7 .................................. Steps 8 ................................ Step 9 .................................. Step 10a,13a ....................... Step 10b,13b ....................... Register Location "Power Down" on page 42 "Power Control 2 (Address 03h)" on page 43 "ADC, Line, HP MUX (Address 08h)" on page 46 "Power Down DSP" on page 50 "Headphone Channel x Mute" on page 57, "Line Channel x Mute" on page 58 "Headphone Volume Control" on page 57, "Line Volume Control" on page 58
4.12.1 Recommended Power-Down Sequence
1. To minimize pops on the headphone and/or line amplifier, each respective analog volume control must first be muted and set to maximum attenuation. Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0] 2. During power down, the CODEC attempts to power down on a zero cross transition of the analog 36 DS773F1
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signal. The zero cross timeout, however, is dependent on the serial port clock domain. Thus, to fully power down, the ADC must briefly power up to enable the zero cross state machine. Follow the remaining steps below to complete the power down sequence. 3. Set bit 5 in register 07h to `1'b. This implements a high impedance state on the serial output ports to avoid possible contention in step 4 if clocks are already applied to the serial port. 4. Configure the serial port I/O control for master operation. Register Controls: M/S 5. Power up either one of the ADC channels. Register Controls: PDN_ADCx 6. Wait 100 ms. 7. Set the PDN bit to `1'b. The CODEC is completely powered down in a low power state. 8. To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be reset to their default state.
Power Down Sequence Step 1a ................................ Step 1b ................................ Step 3 .................................. Step 4 .................................. Step 5 .................................. Step 7 .................................. Register Location "Headphone Volume Control" on page 57, "Line Volume Control" on page 58 "Headphone Channel x Mute" on page 57, "Line Channel x Mute" on page 58 "Miscellaneous Control (Address 07h)" on page 45 "Master/Slave Mode" on page 43 "Power Down ADC x" on page 42 "Power Down" on page 42
4.13
Required Initialization Settings
The current required for various sections in the CODEC must be reduced using the control port compensation strategy shown below. All performance and power consumption measurements were taken with the Control Port Compensation shown below. VA < 2.1 V 1. 2. 3. 4. 5. Write 0x99 to register 0x00. Write 0x30 to register 0x2E. Write 0x07 to register 0x32. Write 0xFF to register 0x33. Write 0xF8 to register 0x34. Write 0xDC to register 0x35. Write 0xFC to register 0x36. Write 0xAC to register 0x37. Write 0xF8 to register 0x3A. 1. 2. 3. 4. 5. 6. 7. 8. 9. VA > 2.1 V Write 0x99 to register 0x00. Write 0x30 to register 0x2E. Write 0x07 to register 0x32. Write 0xFD to register 0x33. Write 0xF8 to register 0x34. Write 0xDC to register 0x35. Write 0xF8 to register 0x36. Write 0x6C to register 0x37. Write 0xF8 to register 0x3A. Current adjustments are made in the following sections: 1. [Enable test register access.] 2. 3. 4. 5. 6. 7. 8. 9. Digital Regulator. ADC. ADC. ADC. Zero Cross Detector. PGA. PGA. DAC. Headphone Amplifier. Headphone & Line Amplifier. Line Amplifier. PGA & ADC. [Disable test register access.].
Control Port Compensation
6. 7. 8. 9. 10. 11. 12. 13. 14.
Write 0xD3 to register 0x3C. 10. Write 0x23 to register 0x3D. 11. Write 0x81 to register 0x3E. 12. Write 0x46 to register 0x3F. Write 0x00 to register 0x00. 13. 14.
Write 0xD3 to register 0x3C. 10. Write 0x23 to register 0x3D. 11. Write 0x81 to register 0x3E. 12. Write 0x46 to register 0x3F. Write 0x00 to register 0x00. 13. 14.
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4.14 Control Port Operation
The control port is used to access the registers allowing the CODEC to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates using an IC interface with the CODEC acting as a slave device.
4.14.1 IC Control
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. The signal timings for a read and write cycle are shown in Figure 21 and Figure 22. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42L55 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 7 bits of the address field are fixed at 1001010. To communicate with the CS42L55, the chip address field, which is the first byte sent to the CS42L55, should match 1001010. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP); the MAP selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42L55 after each input byte is read and is input to the CS42L55 from the microcontroller after each transmitted byte.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
1
0
0
1
0
1
0
0
6
5
4
3
2
ACK START
ACK
ACK
ACK STOP
Figure 21. Control Port Timing, IC Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 0 101
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
START
1
0
0
1
0100
6
5
4
3
2
ACK
ACK START
ACK
ACK
NO ACK
STOP
Figure 22. Control Port Timing, IC Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 22, the write operation is aborted (after the acknowledge for the MAP byte) by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 10010100 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto-increment off. 38 DS773F1
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Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10010101 (chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
4.14.2 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details.
4.14.2.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
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CS42L55 5. REGISTER QUICK REFERENCE
(Default values are shown below the bit names)
IC Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read)
Adr.
01h p 42 02h p 42 03h p 43 04h p 43 05h p 44 06h p 45 07h p 45 08h p 46 09h p 47 0Ah p 48 0Bh p 49 0Ch p 49 0Dh p 50 0Eh p 50 0Fh p 50 10h p 51 11h p 51 12h p 52 13h p 52 14h p 53 15h p 54 16h p 55 17h p 56 18h p 57 19h p 57 1Ah p 57
7 Reserved x Reserved Power Ctl 1 0 PDN_HPB1 Power Ctl 2 1 Reserved Clocking Ctl 1 0 Reserved Clocking Ctl 2 0 Reserved Class H Power 0 Ctl DIGMUX Misc. Ctl 0 ADCBMUX1 ADC, Line, HP 0 MUX HPFB HPF Ctl 1 ADCB=A Misc. ADC Ctl 0 BOOSTA PGAA Vol, MUX 0 BOOSTB PGAB Vol, MUX 0 ADCA Attenua- ADCAATT7 0 tor ADCB Attenua- ADCBATT7 0 tor PDN_DSP Playback Ctl 1 0 AMIXAMUTE ADCMIXA Vol 1 AMIXBMUTE ADCMIXB Vol 1 PMIXAMUTE PCMMIXA Vol 0 PMIXBMUTE PCMMIXB Vol 0 FREQ3 BEEP Freq, 0 On Time OFFTIME2 BEEP Vol, 0 Off Time BEEP1 BEEP, 0 Tone Cfg. TREB3 Tone Ctl 1 MSTAVOL7 Master A Vol 0 MSTBVOL7 Master B Vol 0 HPAMUTE Headphone A 0 Volume
Function ID (Read Only)
6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved REVID2 REVID1 REVID0 x x x x x x x Reserved Reserved Reserved PDN_CHRG PDN_ADCB PDN_ADCA PDN 0 0 0 1 1 1 1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_LINB1 PDN_LINB0 PDN_LINA1 PDN_LINA0 1 1 1 1 1 1 1 Reserved M/S INV_SCLK SCK=MCK1 SCK=MCK0 MCLKDIV2 MCLKDIS 0 0 0 0 0 0 0 Reserved Reserved SPEED1 SPEED0 32kGROUP RATIO1 RATIO0 0 0 0 1 0 1 1 Reserved ADPTPWR1 ADPTPWR0 Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 Reserved Reserved Reserved ANLGZC DIGSFT Reserved FREEZE 0 0 0 1 1 0 0 ADCBMUX0 ADCAMUX1 ADCAMUX0 LINEBMUX LINEAMUX HPBMUX HPAMUX 0 0 0 0 0 0 0 HPFRZB HPFA HPFRZA HPFB_CF1 HPFB_CF0 HPFA_CF1 HPFA_CF0 0 1 0 0 0 0 0 PGAB=A DIGSUM1 DIGSUM0 INV_ADCB INV_ADCA ADCBMUTE ADCAMUTE 0 0 0 0 0 0 0 PGAAMUX PGAAVOL5 PGAAVOL4 PGAAVOL3 PGAAVOL2 PGAAVOL1 PGAAVOL0 0 0 0 0 0 0 0 PGABMUX PGABVOL5 PGABVOL4 PGABVOL3 PGABVOL2 PGABVOL1 PGABVOL0 0 0 0 0 0 0 0 ADCAATT6 ADCAATT5 ADCAATT4 ADCAATT3 ADCAATT2 ADCAATT1 ADCAATT0 0 0 0 0 0 0 0 ADCBATT6 ADCBATT5 ADCBATT4 ADCBATT3 ADCBATT2 ADCBATT1 ADCBATT0 0 0 0 0 0 0 0 DEEMPH Reserved PLYBCKB=A INV_PCMB INV_PCMA MSTBMUTE MSTAMUTE 0 0 0 0 0 0 0 AMIXAVOL6 AMIXAVOL5 AMIXAVOL4 AMIXAVOL3 AMIXAVOL2 AMIXAVOL1 AMIXAVOL0 0 0 0 0 0 0 0 AMIXBVOL6 AMIXBVOL5 AMIXBVOL4 AMIXBVOL3 AMIXBVOL2 AMIXBVOL1 AMIXBVOL0 0 0 0 0 0 0 0 PMIXAVOL6 PMIXAVOL5 PMIXAVOL4 PMIXAVOL3 PMIXAVOL2 PMIXAVOL1 PMIXAVOL0 0 0 0 0 0 0 0 PMIXBVOL6 PMIXBVOL5 PMIXBVOL4 PMIXBVOL3 PMIXBVOL2 PMIXBVOL1 PMIXBVOL0 0 0 0 0 0 0 0 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0 0 0 0 0 0 0 0 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0 0 0 0 0 0 0 0 BEEP0 Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN 0 0 0 0 0 0 0 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0 0 0 0 1 0 0 0 MSTAVOL6 MSTAVOL5 MSTAVOL4 MSTAVOL3 MSTAVOL2 MSTAVOL1 MSTAVOL0 0 0 0 0 0 0 0 MSTBVOL6 MSTBVOL5 MSTBVOL4 MSTBVOL3 MSTBVOL2 MSTBVOL1 MSTBVOL0 0 0 0 0 0 0 0 HPAVOL6 HPAVOL5 HPAVOL4 HPAVOL3 HPAVOL2 HPAVOL1 HPAVOL0 0 0 0 0 0 0 0
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IC Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read)
Adr.
1Bh p 57 1Ch p 58 1Dh p 58 1Eh p 59 1Fh p 59 20h p 60 21h p 60 22h p 61 23h p 62 24h p 62 25h p 63 26h p 64 27h p 64 28h p 65 29h p 66 2Ah p 67
Function Headphone B Volume Line A Volume Line B Volume Analog Input Advisory Vol Digital Input Advisory Vol Channel Mixer & Swap Limit Thresholds Limit Ctl, Release Rate Limiter Attack Rate ALC Enable, Attack Rate ALC Release Rate
7 6 5 4 3 HPBMUTE HPBVOL6 HPBVOL5 HPBVOL4 HPBVOL3 0 0 0 0 0 LINEAMUTE LINEAVOL6 LINEAVOL5 LINEAVOL4 LINEAVOL3 0 0 0 0 0 LINEBMUTE LINEBVOL6 LINEBVOL5 LINEBVOL4 LINEBVOL3 0 0 0 0 0 AINADV7 AINADV6 AINADV5 AINADV4 AINADV3 0 0 0 0 0 DINADV7 DINADV6 DINADV5 DINADV4 DINADV3 0 0 0 0 0 PCMBSWP1 PCMBSWP0 PCMASWP1 PCMASWP0 ADCBSWP1 0 0 0 0 0 LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 0 0 0 0 0 LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 0 1 1 1 1 Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 0 0 0 0 0 ALCB ALCA ALCARATE5 AALCRATE4 ALCARATE3 0 0 0 0 0 Reserved Reserved ALCRRATE5 ALCRRATE4 ALCRRATE3 0 0 1 1 1 ALCMAX2 ALCMAX1 ALCMAX0 ALCMIN2 ALCMIN1 ALC Thresholds 0 0 0 0 0 NGALL NG NGBOOST THRESH2 THRESH1 Noise Gate Ctl 0 0 0 0 0 ALCBSRDIS ALCBZCDIS ALCASRDIS ALCAZCDIS LIMSRDIS ALC, Limiter 0 0 0 0 0 SFT, ZC Disable HPDETECT SPCLKERR DSPBOVFL DSPAOVFL MIXBOVFL Misc. Status 0 0 0 0 0 (Read Only) Reserved Reserved Reserved Reserved CHGFREQ3 Charge Pump 0 0 0 0 0 Freq
2 HPBVOL2 0 LINEAVOL2 0 LINEBVOL2 0 AINADV2 0 DINADV2 0 ADCBSWP0 0 CUSH0 0 LIMRRATE2 1 LIMARATE2 0 ALCARATE2 0 ALCRRATE2 1 ALCMIN0 0 THRESH0 0 Reserved 0 MIXAOVFL 0 CHGFREQ2 1
1 HPBVOL1 0 LINEAVOL1 0 LINEBVOL1 0 AINADV1 0 DINADV1 0 ADCASWP1 0 Reserved 0 LIMRRATE1 1 LIMARATE1 0 ALCARATE1 0 ALCRRATE1 1 Reserved 0 NGDELAY1 0 Reserved 0 ADCBOVFL 0 CHGFREQ1 0
0 HPBVOL0 0 LINEAVOL0 0 LINEBVOL0 0 AINADV0 0 DINADV0 0 ADCASWP0 0 Reserved 0 LIMRRATE0 1 LIMARATE0 0 ALCARATE0 0 ALCRRATE0 1 Reserved 0 NGDELAY0 0 Reserved 0 ADCAOVFL 0 CHGFREQ0 1
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CS42L55 6. REGISTER DESCRIPTION
Except for the chip I.D., revision register, and status register, which are Read Only, all registers are Read/Write. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All Reserved registers must maintain their default state.
IC Address: 1001010[R/W]
6.1
7
Fab I.D. and Revision Register (Address 01h) (Read Only)
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
REVID2
1
REVID1
0
REVID0
Reserved
6.1.1
Chip Revision (Read Only)
CS42L55 revision level.
REVID[2:0] 000 001 Revision Level A0 A1
6.2
7
Power Control 1 (Address 02h)
6
Reserved
5
Reserved
4
Reserved
3
PDN_CHRG
2
PDN_ADCB
1
PDN_ADCA
0
PDN
Reserved
6.2.1
Power Down ADC Charge Pump
Configures the power state of the ADC charge pump. For optimal ADC performance and power consumption, set to `1'b when VA > 2.1 V and set to `0'b when VA < 2.1 V.
PDN_CHRG 0 1 ADC Charge Pump Status Powered Up Powered Down
6.2.2
Power Down ADC x
Configures the power state of ADC channel x.
PDN_ADCx 0 1 ADC Status Powered Up Powered Down
6.2.3
Power Down
Configures the power state of the entire CODEC.
PDN 0 1 CODEC Status Powered Up Powered Down
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6.3
7
PDN_HPB1
Power Control 2 (Address 03h)
6
PDN_HPB0
5
PDN_HPA1
4
PDN_HPA0
3
PDN_LINB1
2
PDN_LINB0
1
PDN_LINA1
0
PDN_LINA0
6.3.1
Headphone Power Control
Configures how the HPDETECT pin, 29, controls the power for the headphone amplifier.
PDN_HPx[1:0] 00 01 10 11 Headphone Status Headphone channel is ON when the HPDETECT pin, 29, is LO. Headphone channel is OFF when the HPDETECT pin, 29, is HI. Headphone channel is ON when the HPDETECT pin, 29, is HI. Headphone channel is OFF when the HPDETECT pin, 29, is LO. Headphone channel is always ON. Headphone channel is always OFF.
6.3.2
Line Power Control
Configures how the HPDETECT pin, 29, controls the power for the line amplifier.
PDN_LINx[1:0] 00 01 10 11 Line Status Line channel is ON when the HPDETECT pin, 29, is LO. Line channel is OFF when the HPDETECT pin, 29, is HI. Line channel is ON when the HPDETECT pin, 29, is HI. Line channel is OFF when the HPDETECT pin, 29, is LO. Line channel is always ON. Line channel is always OFF.
6.4
7
Clocking Control 1 (Address 04h)
6
Reserved
5
M/S
4
INV_SCLK
3
SCK=MCK1
2
SCK=MCK0
1
MCLKDIV2
0
MCLKDIS
Reserved
6.4.1
Master/Slave Mode
Configures the serial port I/O clocking.
M/S 0 1 Application: Serial Port Clocks Slave (Input ONLY) Master (Output ONLY) "Serial Port Clocking" on page 34
6.4.2
SCLK Polarity
Configures the polarity of the SCLK signal.
INV_SCLK 0 1 SCLK Polarity Not Inverted Inverted
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6.4.3 SCLK Equals MCLK
Configures the SCLK signal source and speed for master mode.
SCK=MCK[1:0] 00 01 10 11 Output SCLK Re-timed, bursted signal with minimal speed needed to clock the required data samples Reserved MCLK signal after the MCLK divide (MCLKDIV2) circuit MCLK signal before the MCLK divide (MCLKDIV2) circuit
6.4.4
MCLK Divide By 2
Configures a divide of the input MCLK prior to all internal circuitry.
MCLKDIV2 0 1 Application: MCLK signal into CODEC No divide Divided by 2 "Serial Port Clocking" on page 34
6.4.5
MCLK Disable
Configures the MCLK signal prior to all internal circuitry.
MCLKDIS 0 1 MCLK signal into CODEC On Off; Disables the clock tree to save power when the CODEC is powered down.
Note:
This function should be enabled during power down (PDN=1) ONLY.
6.5
7
Clocking Control 2 (Address 05h)
6
Reserved
5
Reserved
4
SPEED1
3
SPEED0
2
32kGROUP
1
RATIO1
0
RATIO0
Reserved
6.5.1
Speed Mode
Configures the speed mode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for LRCK and SCLK in master mode.
SPEED[1:0] 00 01 10 11 Application: Serial Port Speed Reserved Single-Speed Mode (SSM) Half-Speed Mode (HSM) Quarter-Speed Mode (QSM) "Serial Port Clocking" on page 34
Notes: 1. Slave/Master Mode is determined by the M/S bit in "Master/Slave Mode" on page 43. 2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit ("32 kHz Sample Rate Group" on page 45) and the RATIO[1:0] bits ("Internal MCLK/LRCK Ratio" on page 45). Low sample rates may also affect dynamic range performance in the typical audio band. Refer to the referenced application for more information.
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6.5.2 32 kHz Sample Rate Group
Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.
32kGROUP 0 1 Application: 8 kHz, 16 kHz or 32 kHz sample rate? No Yes "Serial Port Clocking" on page 34
6.5.3
Internal MCLK/LRCK Ratio
Configures the internal MCLK/LRCK ratio.
RATIO[1:0] 00 01 10 11 Application: Internal MCLK Cycles per LRCK Reserved 125 Reserved 136 "Serial Port Clocking" on page 34
6.6
7
Class H Power Control (Address 06h)
6
Reserved
5
ADPTPWR1
4
ADPTPWR0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Reserved
6.6.1
Adaptive Power Adjustment
Configures how the power to the headphone and line amplifiers adapts to the output signal level.
ADPTPWR[1:0] 00 01 10 11 Application: Power Supply Adapted to volume setting; Voltage level is determined by the sum of the relevant volume settings Fixed - Headphone and Line Amp supply = +/-VCP/2 Fixed - Headphone and Line Amp supply = +/-VCP Adapted to Signal; Voltage level is dynamically determined by the output signal "Class H Amplifier" on page 27
6.7
7
Miscellaneous Control (Address 07h)
6
Reserved
5
Reserved
4
Reserved
3
ANLGZC
2
DIGSFT
1
Reserved
0
FREEZE
DIGMUX
6.7.1
Digital MUX
Selects the signal source for the ADC serial port.
DIGMUX 0 1 SDOUT Signal Source ADC DSP Mix
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6.7.2 Analog Zero Cross
Configures when the signal level changes occur for the analog volume controls.
ANLGZCx 0 1 Volume Changes Do not occur on a zero crossing Occur on a zero crossing Affected Analog Volume Controls PGAx_VOL[5:0] ("PGAx Volume" on page 49) HPxMUTE ("Headphone Channel x Mute" on page 57) HPxVOL[6:0] ("Headphone Volume Control" on page 57) LINExMUTE ("Line Channel x Mute" on page 58) LINExVOL[6:0] ("Line Volume Control" on page 58)
Note: If the signal does not encounter a zero crossing, the requested volume change will occur after a timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate).
6.7.3
Digital Soft Ramp
Configures an incremental volume ramp from the current level to the new level at the specified rate.
DIGSFT 0 Volume Changes Do not occur with a soft ramp Affected Digital Volume Controls ADCxMUTE ("ADC Mute" on page 48) ADCxATT[7:0] ("ADCx Volume" on page 50) AMIXxMUTE ("ADC Mixer Channel x Mute" on page 51) AMIXxVOL[6:0] ("ADC Mixer Channel x Volume" on page 51) PMIXxMUTE ("PCM Mixer Channel x Mute" on page 52) PMIXxVOL[6:0] ("PCM Mixer Channel x Volume" on page 52) MSTxMUTE ("Master Playback Mute" on page 51) MSTxVOL[7:0] ("Master Volume Control" on page 57)
1
Occur with a soft ramp
Ramp Rate:
1/8 dB every LRCK cycle
6.7.4
Freeze Registers
Configures a hold on all register settings.
FREEZE 0 1 Control Port Status Register changes take effect immediately Modifications may be made to all control port registers without the changes taking effect until after the FREEZE is disabled.
6.8
7
ADC, Line, HP MUX (Address 08h)
6
ADCBMUX0
5
ADCAMUX1
4
ADCAMUX0
3
LINEBMUX
2
LINEAMUX
1
HPBMUX
0
HPAMUX
ADCBMUX1
6.8.1
ADC x Input Select
Selects the specified analog input signal into ADCx.
ADCxMUX[1:0] 00 01 10 11 Selected Input to ADCx PGAx - Use PGAxMUX bit ("PGA x Input Select" on page 49) to select an input channel. AIN1x; PGA is bypassed AIN2x; PGA is bypassed Reserved
Note:
Pseudo-differential inputs are not available when the PGA is bypassed.
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6.8.2 Line Input Select
Selects the specified analog input signal into line amplifier x.
LINExMUX 0 1 Selected Input to Line Amplifier Ch. x DACx PGAx - Use PGAxMUX bit ("PGA x Input Select" on page 49) to select an input channel.
Note:
The PGA path must not be selected while the Line Amplifier is powered down.
6.8.3
Headphone Input Select
Selects the specified analog input signal into headphone amplifier x.
HPxMUX 0 1 Selected Input to HP Amplifier Ch. x DACx PGAx - Use PGAxMUX bit ("PGA x Input Select" on page 49) to select an input channel.
Note:
The PGA path must not be selected while the Headphone Amplifier is powered down.
6.9
7
HPF Control (Address 09h)
6
HPFRZB
5
HPFA
4
HPFRZA
3
HPFB_CF1
2
HPFB_CF0
1
HPFA_CF1
0
HPFA_CF0
HPFB
6.9.1
ADCx High-Pass Filter
Configures the internal high-pass filter after ADCx.
HPFx 0 1 High Pass Filter Status Disabled Enabled
6.9.2
ADCx High-Pass Filter Freeze
Configures the high pass filter's digital DC subtraction and/or calibration after ADCx.
HPFRZx 0 1 High Pass Filter Digital Subtraction Continuous DC Subtraction Frozen DC Subtraction
6.9.3
HPF x Corner Frequency
Sets the corner frequency (-3 dB point) for the internal High-Pass Filter (HPF).
HPFx_CF[1:0] 00 01 10 11 HPF Corner Frequency Setting (Fs=48 kHz) 1.8 Hz 119 Hz 236 Hz 464 Hz
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CS42L55
6.10
7
ADCB=A
Misc. ADC Control (Address 0Ah)
6
PGAB=A
5
DIGSUM1
4
DIGSUM0
3
INV_ADCB
2
INV_ADCA
1
ADCBMUTE
0
ADCAMUTE
6.10.1 ADC Channel B=A
Configures independent or ganged volume control of the ADC and the ALC.
ADCB=A 0 1 Single Volume Control Disabled Enabled
6.10.2 PGA Channel B=A
Configures independent or ganged volume control of the PGA.
PGAB=A 0 1 Single Volume Control Disabled Enabled
6.10.3 Digital Sum
Configures a mix/swap of ADCA and ADCB.
DIGSUM[1:0] 00 01 10 11 Serial Output Signal Left Channel ADCA (ADCA + ADCB)/2 (ADCA - ADCB)/2 ADCB Right Channel ADCB (ADCA + ADCB)/2 (ADCA - ADCB)/2 ADCA
6.10.4 Invert ADC Signal Polarity
Configures the polarity of the ADC signal.
INV_ADCx 0 1 ADC Signal Polarity Not Inverted Inverted
6.10.5 ADC Mute
Configures a digital mute on ADC channel x.
ADCxMUTE 0 1 ADC Mute Not muted. Muted
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6.11
7
BOOSTx
PGA x MUX, Volume: PGA A (Address 0Bh) & PGA B (Address 0Ch)
6
PGAxMUX
5
PGAxVOL5
4
PGAxVOL4
3
PGAxVOL3
2
PGAxVOL2
1
PGAxVOL1
0
PGAxVOL0
6.11.1 Boostx
Configures a +20 dB boost on channel x.
BOOSTx 0 1 +20 dB Boost No boost applied +20 dB boost applied
6.11.2
PGA x Input Select
Selects the specified analog input signal into PGA channel x.
PGAxMUX 0 1 Selected Input to PGAx AIN1x AIN2x
Note: For pseudo-differential inputs, the CODEC automatically chooses the respective pseudo-ground (AIN1REF or AIN2REF) for each input selection.
6.11.3
PGAx Volume
Sets the volume/gain of the Programmable Gain Amplifier (PGA).
PGAxVOL[5:0] 01 1111 ... 01 1000 ... 00 0001 00 0000 11 1111 ... 11 0100 ... 10 0000 Step Size: Volume 12 dB ... 12 dB ... +0.5 dB 0 dB -0.5 dB ... -6.0 dB ... -6.0 dB 0.5 dB
Notes: 1. Refer to Figure 23 and Figure 24 on page 69 for differential and integral nonlinearity (DNL and INL).
DS773F1
49
CS42L55
6.12
7
ADCxATT7
ADCx Attenuator Control: ADCAATT (Address 0Dh) & ADCBATT (Address 0Eh)
6
ADCxATT6
5
ADCxATT5
4
ADCxATT4
3
ADCxATT3
2
ADCxATT2
1
ADCxATT1
0
ADCxATT0
6.12.1 ADCx Volume
Sets the volume of the ADC signal.
ADCxATT[7:0] 0111 1111 ... 0000 0000 1111 1111 1111 1110 ... 1010 0000 ... 1000 0000 Step Size: Volume 0 dB ... 0 dB -1.0 dB -2.0 dB ... -96.0 dB ... -96.0 dB 1.0 dB
6.13
7
Playback Control 1 (Address 0Fh)
6
DEEMPH
5
Reserved
4
PLYBCKB=A
3
INV_PCMB
2
INV_PCMA
1
MSTBMUTE
0
MSTAMUTE
PDN_DSP
6.13.1 Power Down DSP
Configures the power state of the DSP Engine.
PDNDSP 0 1 DSP Status Powered Up Powered Down DSP Engine Controls/Blocks AMIXxMUTE ("ADC Mixer Channel x Mute" on page 51) AMIXxVOL[6:0] ("ADC Mixer Channel x Volume" on page 51) PMIXxMUTE ("PCM Mixer Channel x Mute" on page 52) PMIXxVOL[6:0] ("PCM Mixer Channel x Volume" on page 52) Beep Generator, Tone Control, De-Emphasis
6.13.2 HP/Line De-Emphasis
Configures a 15s/50s digital de-emphasis filter response on the headphone and line outputs.
DEEMPH 0 1 De-Emphasis Status Diabled Enabled
6.13.3 Playback Channels B=A
Configures independent or ganged volume control of all playback channels.
PLYBCKB=A 0 1 Single Volume Control for all Playback Channels Disabled; Independent channel control. Enabled; Ganged channel control. Channel A volume control controls channel B volume.
Note: This function does not affect the AMIXBMUTE, PMIXBMUTE or MSTBMUTE control. When muting channel A in a ganged scenario, the MUTEB must also be enabled. Muting channel A without muting channel B in a ganged scenario may cause clipping on channel B. 50 DS773F1
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6.13.4 Invert PCM Signal Polarity
Configures the polarity of the digital input signal.
INV_PCMx 0 1 PCM Signal Polarity Not Inverted Inverted
6.13.5 Master Playback Mute
Configures a digital mute on the master volume control for channel x.
MSTxMUTE 0 1 Master Mute Not muted. Muted
6.14
7
ADCx Mixer Volume: ADCA (Address 10h) & ADCB (Address 11h)
6
AMIXxVOL6
5
AMIXxVOL5
4
AMIXxVOL4
3
AMIXxVOL3
2
AMIXxVOL2
1
AMIXxVOL1
0
AMIXxVOL0
AMIXxMUTE
6.14.1 ADC Mixer Channel x Mute
Configures a digital mute on the ADC mix in the DSP Engine.
AMIXxMUTE 0 1 ADC Mixer Mute Disabled Enabled
6.14.2 ADC Mixer Channel x Volume
Sets the volume/gain of the ADC mix in the DSP Engine.
AMIXxVOL[6:0] 001 1000 ... 000 0001 000 0000 111 1111 ... 001 1001 Step Size: Volume +12.0 dB ... +0.5 dB 0 dB -0.5 dB ... -51.5 dB 0.5 dB
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6.15
7
PMIXxMUTE
PCMx Mixer Volume: PCMA (Address 12h) & PCMB (Address 13h)
6
PMIXxVOL6
5
PMIXxVOL5
4
PMIXxVOL4
3
PMIXxVOL3
2
PMIXxVOL2
1
PMIXxVOL1
0
PMIXxVOL0
6.15.1 PCM Mixer Channel x Mute
Configures a digital mute on the PCM mix from the serial data input (SDIN) to the DSP Engine.
PMIXxMUTE 0 1 PCM Mixer Mute Disabled Enabled
6.15.2 PCM Mixer Channel x Volume
Sets the volume/gain of the PCM mix from the serial data input (SDIN) to the DSP Engine.
PMIXxVOL[6:0] 001 1000 ... 000 0001 000 0000 111 1111 ... 001 1001 Step Size: Volume +12.0 dB ... +0.5 dB 0 dB -0.5 dB ... -51.5 dB 0.5 dB
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6.16
7
FREQ3
Beep Frequency & On Time (Address 14h)
6
FREQ2
5
FREQ1
4
FREQ0
3
ONTIME3
2
ONTIME2
1
ONTIME1
0
ONTIME0
6.16.1 Beep Frequency
Sets the frequency of the beep signal.
FREQ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Application: Frequency (Fs = 12, 24 or 48 kHz) 254.76 Hz 509.51 Hz 571.65 Hz 651.04 Hz 689.34 Hz 756.04 Hz 869.45 Hz 976.56 Hz 1019.02 Hz 1171.88 Hz 1302.08 Hz 1378.67 Hz 1562.50 Hz 1674.11 Hz 1953.13 Hz 2130.68 Hz "Beep Generator" on page 31
Notes: 1. This setting must not change when BEEP is enabled. 2. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode.
DS773F1
53
CS42L55
6.16.2 Beep On Time
Sets the on duration of the beep signal.
ONTIME[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Application: On Time (Fs = 12, 24 or 48 kHz) ~86 ms ~430 ms ~780 ms ~1.20 s ~1.50 s ~1.80 s ~2.20 s ~2.50 s ~2.80 s ~3.20 s ~3.50 s ~3.80 s ~4.20 s ~4.50 s ~4.80 s ~5.20 s "Beep Generator" on page 31
Notes: 1. This setting must not change when BEEP is enabled. 2. Beep on time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode.
6.17
7
Beep Volume & Off Time (Address 15h)
6
OFFTIME1
5
OFFTIME0
4
BPVOL4
3
BPVOL3
2
BPVOL2
1
BPVOL1
0
BPVOL0
OFFTIME2
6.17.1 Beep Off Time
Sets the off duration of the beep signal.
OFFTIME[2:0] 000 001 010 011 100 101 110 111 Application: Off Time (Fs = 12, 24 or 48 kHz) ~1.23 s ~2.58 s ~3.90 s ~5.20 s ~6.60 s ~8.05 s ~9.35 s ~10.80 s "Beep Generator" on page 31
Notes: 1. This setting must not change when BEEP and/or REPEAT is enabled. 2. Beep off time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. 54 DS773F1
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6.17.2 Beep Volume
Sets the volume of the beep signal.
BPVOL[4:0] 00110 *** 00000 11111 11110 *** 00111 Step Size: Application: Gain +12.0 dB *** 0 dB -2 dB -4 dB *** -50 dB 2 dB "Beep Generator" on page 31
Note:
This setting must not change when BEEP is enabled.
6.18
7
Beep & Tone Configuration (Address 16h)
6
BEEP0
5
Reserved
4
TREBCF1
3
TREBCF0
2
BASSCF1
1
BASSCF0
0
TCEN
BEEP1
6.18.1 Beep Configuration
Configures a beep mixed with the HP and Line output.
BEEP[1:0] 00 01 10 11 Application: Beep Occurrence Off Single Multiple Continuous "Beep Generator" on page 31
Notes: 1. When used in analog pass through mode, the output alternates between the signal from the PGA and the beep signal. The beep signal does not mix with the analog signal from the PGA. 2. Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON for the maximum ONTIME duration.
6.18.2 Treble Corner Frequency
Sets the corner frequency for the treble shelving filter.
TREBCF[1:0] 00 01 10 11 Treble Corner Frequency Setting 5 kHz 7 kHz 10 kHz 15 kHz
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CS42L55
6.18.3 Bass Corner Frequency
Sets the corner frequency for the bass shelving filter.
BASSCF[1:0] 00 01 10 11 Bass Corner Frequency Setting 50 Hz 100 Hz 200 Hz 250 Hz
6.18.4 Tone Control Enable
Configures the treble and bass activation.
TCEN 0 1 Bass and Treble Control Disabled Enabled
6.19
7
Tone Control (Address 17h)
6
TREB2
5
TREB1
4
TREB0
3
BASS3
2
BASS2
1
BASS1
0
BASS0
TREB3
6.19.1 Treble Gain
Sets the gain of the treble shelving filter.
TREB[3:0] 0000 *** 0111 1000 1001 *** 1111 Step Size: Gain Setting +12.0 dB *** +1.5 dB 0 dB -1.5 dB *** -10.5 dB 1.5 dB
6.19.2 Bass Gain
Sets the gain of the bass shelving filter.
BASS[3:0] 0000 *** 0111 1000 1001 *** 1111 Step Size: Gain Setting +12.0 dB *** +1.5 dB 0 dB -1.5 dB *** -10.5 dB 1.5 dB
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6.20
7
MSTxVOL7
Master Volume Control: MSTA (Address 18h) & MSTB (Address 19h)
6
MSTxVOL6
5
MSTxVOL5
4
MSTxVOL4
3
MSTxVOL3
2
MSTxVOL2
1
MSTxVOL1
0
MSTxVOL0
6.20.1 Master Volume Control
Sets the volume of the signal out the DSP.
MSTxVOL[7:0] 0001 1000 *** 0000 0000 1111 1111 1111 1110 *** 0011 0100 *** 0001 1001 Step Size: Master Volume +12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -102 dB *** -102 dB 0.5 dB
6.21
7
Headphone Volume Control: HPA (Address 1Ah) & HPB (Address 1Bh)
6
HPxVOL6
5
HPxVOL5
4
HPxVOL4
3
HPxVOL3
2
HPxVOL2
1
HPxVOL1
0
HPxVOL0
HPxMUTE
6.21.1 Headphone Channel x Mute
Configures an analog mute on the headphone amplifier.
HPxMUTE 0 1 HP Amp Mute Disabled Enabled
6.21.2 Headphone Volume Control
Sets the volume of the signal out of the headphone amplifier.
HPxVOL[6:0] 0111111 ... 0001100 ... 0000001 0000000 1111111 ... 1000100 ... 1000000 Step Size: Heaphone Volume 12 dB ... 12 dB ... +1.0 dB 0 dB -1.0 dB ... -60.0 dB (Actual volume is approximately -58 dB. (Note 1)) ... -60.0 dB (Actual volume is approximately -58 dB. (Note 1)) 1.0 dB
Note: 1. The step size may deviate from 1.0 dB. Refer to Figure 25 and Figure 26 on page 69. DS773F1 57
CS42L55
6.22
7
LINExMUTE
Line Volume Control: LINEA (Address 1Ch) & LINEB (Address 1Dh)
6
LINExVOL6
5
LINExVOL5
4
LINExVOL4
3
LINExVOL3
2
LINExVOL2
1
LINExVOL1
0
LINExVOL0
6.22.1 Line Channel x Mute
Configures an analog mute on the line amplifier.
LINExMUTE 0 1 HP Amp Mute Disabled Enabled
6.22.2 Line Volume Control
Sets the volume of the signal out of the line amplifier.
LINExVOL[6:0] 0111111 ... 0001100 ... 0000001 0000000 1111111 ... 1000100 ... 1000000 Step Size: Line Volume 12 dB ... 12 dB ... +1.0 dB 0 dB -1.0 dB ... -60.0 dB (Actual volume is approximately -58 dB. (Note 1)) ... -60.0 dB (Actual volume is approximately -58 dB. (Note 1)) 1.0 dB
Note: 1. The step size may deviate from 1.0 dB. Refer to Figure 25 on page 69 and Figure 26 on page 69.
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6.23
7
AINADV7
Analog Input Advisory Volume (Address 1Eh)
6
AINADV6
5
AINADV5
4
AINADV4
3
AINADV3
2
AINADV2
1
AINADV1
0
AINADV0
6.23.1 Analog Input Advisory Volume
Defines the maximum analog input volume level used by the class H controller to determine the appropriate supply for the HP and Line amplifiers.
AINADV[7:0] 0001 1000 *** 0000 0001 0000 0000 1111 1111 1111 1110 *** 0011 0100 *** 0001 1001 Step Size: Defined Input Volume Reserved *** Reserved 0 dB -0.5 dB -1.0 dB *** -102 dB *** -102 dB 0.5 dB
6.24
7
Digital Input Advisory Volume (Address 1Fh)
6
DINADV6
5
DINADV5
4
DINADV4
3
DINADV3
2
DINADV2
1
DINADV1
0
DINADV0
DINADV7
6.24.1 Digital Input Advisory Volume
Defines the maximum digital input volume level used by the class H controller to determine the appropriate supply for the HP and Line amplifiers.
DINADV[7:0] 0001 1000 *** 0000 0001 0000 0000 1111 1111 1111 1110 *** 0011 0100 *** 0001 1001 Step Size: Defined Input Volume Reserved *** Reserved 0 dB -0.5 dB -1.0 dB *** -102 dB *** -102 dB 0.5 dB
Note: Between the headphone and line, the final output voltage from the charge pump is dictated by the highest required advisory volume. When any respective amplifier is powered down, the charge pump's voltage automatically adjusts to the appropriate level.
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CS42L55
6.25
7
PCMBSWP1
ADC & PCM Channel Mixer (Address 20h)
6
PCMBSWP0
5
PCMASWP1
4
PCMASWP0
3
ADCBSWP1
2
ADCBSWP0
1
ADCASWP1
0
ADCASWP0
6.25.1 PCM Mix Channel Swap
Configures a mix/swap of the PCM Mix to the headphone/line outputs.
PCMxSWP[1:0] 00 01 10 11 PCM Mix to HP/LINEOUTA Left (Left + Right)/2 Right PCM Mix to HP/LINEOUTB Right (Left + Right)/2 Left
6.25.2 ADC Mix Channel Swap
Configures a mix/swap of the ADC Mix to the headphone/line outputs. .
ADCxSWP[1:0] 00 01 10 11 ADC Mix to HP/LINEOUTA Channel Left (Left + Right)/2 Right ADC Mix to HP/LINEOUTB Channel Right (Left + Right)/2 Left
6.26
7
Limiter Min/Max Thresholds (Address 21h)
6
LMAX1
5
LMAX0
4
CUSH2
3
CUSH1
2
CUSH0
1
Reserved
0
Reserved
LMAX2
6.26.1 Limiter Maximum Threshold
Sets the maximum level, below full-scale, at which to limit and attenuate the output signal at the attack rate (LIMARATE - "Limiter Release Rate" on page 62).
LMAX[2:0] 000 001 010 011 100 101 110 111 Application: Threshold Setting 0 dB -3 dB -6 dB -9 dB -12 dB -18 dB -24 dB -30 dB "Limiter" on page 32
Note: Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack.
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6.26.2 Limiter Cushion Threshold
Sets the minimum level at which to disengage the Limiter's attenuation at the release rate (LIMRRATE "Limiter Release Rate" on page 62) until levels lie between the LMAX and CUSH thresholds.
CUSH[2:0] 000 001 010 011 100 101 110 111 Application: Threshold Setting 0 dB -3 dB -6 dB -9 dB -12 dB -18 dB -24 dB -30 dB "Limiter" on page 32
Note:
This setting is usually set slightly below the LMAX threshold.
6.27
7
Limiter Control, Release Rate (Address 22h)
6
LIMIT_ALL
5
LIMRRATE5
4
LIMRRATE4
3
LIMRRATE3
2
LIMRRATE2
1
LIMRRATE1
0
LIMRRATE0
LIMIT
6.27.1 Peak Detect and Limiter
Configures the peak detect and limiter circuitry.
LIMIT 0 1 Application: Limiter Status Disabled Enabled "Limiter" on page 32
6.27.2 Peak Signal Limit All Channels
Sets how channels are attenuated when the limiter is enabled.
LIMIT_ALL Limiter action: Apply the necessary attenuation on a specific channel only when the signal amplitudes on that specific channel rises above LMAX. Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below CUSH. Apply the necessary attenuation on BOTH channels when the signal amplitudes on any ONE channel rises above LMAX. Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH. "Limiter" on page 32
0
1 Application:
DS773F1
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CS42L55
6.27.3 Limiter Release Rate
Sets the rate at which the limiter releases the digital attenuation from levels below the CUSH[2:0] threshold ("Limiter Cushion Threshold" on page 61) and returns the analog output level to the MSTxVOL[7:0] ("Master Volume Control" on page 57) setting.
LIMRRATE[5:0] 00 0000 *** 11 1111 Application: Release Time Fastest Release *** Slowest Release "Limiter" on page 32
Note: The limiter release rate is user-selectable but is also a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 46) setting unless the disable bit ("Limiter Soft Ramp Disable" on page 66) is enabled.
6.28
7
Limiter Attack Rate (Address 23h)
6
Reserved
5
LIMARATE5
4
LIMARATE4
3
LIMARATE3
2
LIMARATE2
1
LIMARATE1
0
LIMARATE0
Reserved
6.28.1 Limiter Attack Rate
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold ("Limiter Maximum Threshold" on page 60).
LIMARATE[5:0] 00 0000 *** 11 1111 Application: Attack Time Fastest Attack *** Slowest Attack "Limiter" on page 32
Note: The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 46) setting unless the disable bit ("Limiter Soft Ramp Disable" on page 66) is enabled.
6.29
7
ALC Enable & Attack Rate (Address 24h)
6
ALCA
5
ALCARATE5
4
AALCRATE4
3
ALCARATE3
2
ALCARATE2
1
ALCARATE1
0
ALCARATE0
ALCB
6.29.1 ALCx
Configures the automatic level controller (ALC).
ALC 0 1 Application: ALC Status Disabled Enabled "Automatic Level Control (ALC)" on page 24
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6.29.2 ALC Attack Rate
Sets the rate at which the ALC applies analog and/or digital attenuation from levels above the AMAX[2:0] threshold ("ALC Maximum Threshold" on page 64).
ALCARATE[5:0] 00 0000 *** 11 1111 Application: Attack Time Fastest Attack *** Slowest Attack "Automatic Level Control (ALC)" on page 24
Note: The ALC attack rate is user-selectable but is also a function of the sampling frequency, Fs, the ANLGZCx ("Analog Zero Cross" on page 46) and the DIGSFT ("Digital Soft Ramp" on page 46) setting unless the respective disable bit ("ALCx Soft Ramp Disable" on page 65 or "ALCx Zero Cross Disable" on page 65) is enabled.
6.30
7
ALC Release Rate (Address 25h)
6
Reserved
5
ALCRRATE5
4
ALCRRATE4
3
ALCRRATE3
2
ALCRRATE2
1
ALCRRATE1
0
ALCRRATE0
Reserved
6.30.1 ALC Release Rate
Sets the rate at which the ALC releases the analog and/or digital attenuation from levels below the MIN[2:0] threshold ("Limiter Cushion Threshold" on page 61) and returns the signal level to the PGAxVOL[5:0] ("PGAx Volume" on page 49) and ADCxVOL[7:0] ("ADCx Volume" on page 50) setting.
ALCRRATE[5:0] 00 0000 *** 11 1111 Application: Release Time Fastest Release *** Slowest Release "Automatic Level Control (ALC)" on page 24
Notes: 1. The ALC release rate is user-selectable but is also a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 46) and ANLGZCx ("Analog Zero Cross" on page 46) setting. 2. The Release Rate setting must always be slower than the Attack Rate.
DS773F1
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CS42L55
6.31
7
ALCMAX2
ALC Threshold (Address 26h)
6
ALCMAX1
5
ALCMAX0
4
ALCMIN2
3
ALCMIN1
2
ALCMIN0
1
Reserved
0
Reserved
6.31.1 ALC Maximum Threshold
Sets the maximum level, below full-scale, at which to limit and attenuate the input signal at the attack rate (ALCARATE - "ALC Attack Rate" on page 63).
MAX[2:0] 000 001 010 011 100 101 110 111 Application: Threshold Setting 0 dB -3 dB -6 dB -9 dB -12 dB -18 dB -24 dB -30 dB "Automatic Level Control (ALC)" on page 24
6.31.2 ALC Minimum Threshold
Sets the minimum level at which to disengage the ALC's attenuation or amplify the input signal at the release rate (ALCRRATE - "ALC Release Rate" on page 63) until levels lie between the ALCMAX and ALCMIN thresholds.
ALCMIN[2:0] 000 001 010 011 100 101 110 111 Application: Threshold Setting 0 dB -3 dB -6 dB -9 dB -12 dB -18 dB -24 dB -30 dB "Automatic Level Control (ALC)" on page 24
Note:
This setting is usually set slightly below the ALCMAX threshold.
6.32
7
Noise Gate Control (Address 27h)
6
NG
5
NG_BOOST
4
THRESH2
3
THRESH1
2
THRESH0
1
NGDELAY1
0
NGDELAY0
NGALL
6.32.1 Noise Gate All Channels
Sets which channels are attenuated when clipping on any single channel occurs.
NGALL 0 1 Noise Gate triggered by: Individual channel; Any channel that falls below the threshold setting triggers the noise gate attenuation for ONLY that channel. Both channels A & B; Both channels must fall below the threshold setting for the noise gate attenuation to take effect.
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6.32.2 Noise Gate Enable
Configures the noise gate.
NG 0 1 Noise Gate Status Disabled Enabled
6.32.3 Noise Gate Threshold and Boost
THRESH sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96 dB. NG_BOOST configures a +30 dB boost to the threshold settings.
THRESH[2:0] 000 001 010 011 100 101 110 111 Minimum Setting (NG_BOOST = `0'b) -64 dB -67 dB -70 dB -73 dB -76 dB -82 dB Reserved Reserved Minimum Setting (NG_BOOST = `1'b) -34 dB -36 dB -40 dB -43 dB -46 dB -52 dB -58 dB -64 dB
6.32.4 Noise Gate Delay Timing
Sets the delay time before the noise gate attacks.
NGDELAY[1:0] 00 01 10 11 Delay Setting 50 ms 100 ms 150 ms 200 ms
Note: The Noise Gate attack rate is a function of the sampling frequency, Fs, and the DIGSFT ("Digital Soft Ramp" on page 46) setting unless the disable bit ("ALCx Soft Ramp Disable" on page 65) is enabled.
6.33
7
ALC and Limiter Soft Ramp, Zero Cross Disables (Address 28h)
6
ALCBZCDIS
5
ALCASRDIS
4
ALCAZCDIS
3
LIMSRDIS
2
1
Reserved
0
Reserved
ALCBSRDIS
6.33.1 ALCx Soft Ramp Disable
Configures an override of the analog soft ramp setting.
ALCxSRDIS 0 1 ALC Soft Ramp Disable OFF; ALC Attack Rate is dictated by the DIGSFT ("Digital Soft Ramp" on page 46) setting ON; ALC volume changes take effect in one step, regardless of the DIGSFT setting.
6.33.2 ALCx Zero Cross Disable
Configures an override of the analog zero cross setting.
ALCxZCDIS 0 1 ALC Zero Cross Disable OFF; ALC Attack Rate is dictated by the ANLGZC ("Analog Zero Cross" on page 46) setting ON; ALC volume changes take effect at any time, regardless of the ANLGZC setting.
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6.33.3 Limiter Soft Ramp Disable
Configures an override of the digital soft ramp setting.
LIMSRDIS 0 1 Limiter Soft Ramp Disable OFF; Limiter Attack Rate is dictated by the DIGSFT ("Digital Soft Ramp" on page 46) setting ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.
6.34
Status (Address 29h) (Read Only)
For bits [6:0] in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A"0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets these bits to 0.
7 6
SPCLKERR
5
DSPBOVFL
4
DSPAOVFL
3
MIXBOVFL
2
MIXAOVFL
1
ADCBOVFL
0
ADCAOVFL
HPDETECT
6.34.1 HPDETECT Pin Status (Read Only)
Indicates the status of the HPDETECT pin.
HPDETECT 0 1 Pin State Low High
6.34.2 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
SPCLKERR 0 1 Application: Serial Port Clock Status: MCLK/LRCK ratio is valid. MCLK/LRCK ratio is not valid. "Serial Port Clocking" on page 34
Note: nizes.
On initial power up and application of clocks, this bit will report `1'b as the serial port re-synchro-
6.34.3 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
DSPxOVFL 0 1 DSP Overflow Status: No digital clipping has occurred in the data path after the DSP. Digital clipping has occurred in the data path after the DSP.
6.34.4 MIXx Overflow (Read Only)
Indicates the over-range status in the PCM mix data path.
MIXxOVFL 0 1 PCM Overflow Status: No digital clipping has occurred in the data path of the ADC and PCM mix of the DSP. Digital clipping has occurred in the data path of the ADC and PCM mix of the DSP.
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6.34.5 ADCx Overflow (Read Only)
Indicates the over-range status in the ADC signal path.
ADCxOVFL 0 1 ADC Overflow Status: No clipping has occurred anywhere in the ADC signal path. Clipping has occurred in the ADC signal path.
6.35
7
Charge Pump Frequency (Address 2Ah)
6
Reserved
5
Reserved
4
Reserved
3
CHGFREQ3
2
CHGFREQ2
1
CHGFREQ1
0
CHGFREQ0
Reserved
6.35.1 Charge Pump Frequency
Sets the charge pump frequency on FLYN and FLYP.
CHGFREQ[3:0] 0000 ... 0101 ... 1111 Formula: 15 Frequency = 1.5 MHz/(N+2) 5 N 0
Note: The output THD+N performance improves at higher frequencies; power consumption increases at higher frequencies.
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CS42L55 7. PCB LAYOUT CONSIDERATIONS
7.1 Power Supply
As with any high-resolution converter, the CS42L55 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 10 shows the recommended power arrangements, with VA and VCP connected to clean supplies. VLDO, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VLDO may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VLDO.
7.2
Grounding
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS42L55 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS42L55 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+, VQ, +VHPFILT and -VHPFILT capacitors must be positioned to minimize the electrical path from each respective pin to AGND. The CDB42L55 evaluation board demonstrates the optimum layout and power supply arrangements.
7.3
QFN Thermal Pad
The CS42L55 comes in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CDB42L55 evaluation board demonstrates the optimum thermal pad and via configuration.
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CS42L55 8. ANALOG VOLUME NON-LINEARITY (DNL & INL)
0.52 Actual Step Size, dB 0.5 0.48 0.46 0.44 0.42 0.4 -1 0
Actual Output Volume, dB 12 10 8 6 4 2 0 -2 -4 -6 -6 -5 -4 -3 -2 -1 -8 0 123456 PGA Volume Setting 7 8 9 10 11 12
-6
-5
-4
-3
-2
12345 PGA Volume Setting
6
7
8
9
10 11
Figure 23. PGA Step Size vs. Volume Setting
Figure 24. PGA Output Volume vs. Volume Setting
Actual Output Volume, dB
1
10 0 -1 0 -2 0 -3 0 -4 0 -5 0 -6 0
Actual Step Size, dB
0.8 0.6 0.4 0.2 0 -60 -50 -40 -30 -20 -10 0 +10 +20
-6 0
-5 0
-4 0
-3 0
-2 0
-1 0
0
10
20
HP/Line Volume Setting
H P /L in e V o lu m e S e ttin g
Figure 25. HP/Line Step Size vs. Volume Setting
Figure 26. HP/Line Output Volume vs. Volume Setting
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CS42L55 9. ADC & DAC DIGITAL FILTERS
0
0.25
-10
0.2
-20
0.15 0.1
-30
Amplitude dB
0 -0.05 -0.1
Amplitude dB
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0.05
-40
-50
-60
-70
-0.15 -0.2 -0.25
-80
-90
-100
Frequency (normalized to Fs)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (normalized to Fs)
Figure 27. ADC Passband Ripple
0 -10
Figure 28. ADC Stopband Rejection
0 -1
-20
-2
-30
-3
Amplitude dB
-40
Amplitude dB
-4
-50
-5
-60
-6
-70
-7
-80
-8
-90
-9
-100 0.4
0.43
0.46
0.49
0.52
0.55
0.58
0.61
0.64
-10 0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 29. ADC Transition Band
0.03
Figure 30. ADC Transition Band Detail
0 -10
0.02 -20 0.01
-30
Magnitude (dB)
Magnitude (dB)
0
-40
-0.01
-50
-0.02
-60
-0.03
-70
-80 -0.04 -90 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 frequency (Normalized to Fs) 0.35 0.4 0.45 0 0.1 0.2 0.3 0.4 0.5 0.6 frequency (Normalized to Fs) 0.7 0.8 0.9 1
Figure 31. DAC Passband Ripple
0
Figure 32. DAC Stopband
0
-10
-10
-20
-20
Magnitude (dB)
-30
Magnitude (dB)
0.42 0.44 0.46 0.48 0.5 0.52 0.54 frequency (Normalized to Fs) 0.56 0.58 0.6
-30
-40
-40
-50
-50
-60
-60
0.4
0.45
0.46
0.47
0.48
0.49 0.5 0.51 frequency (Normalized to Fs)
0.52
0.53
0.54
Figure 33. DAC Transition Band
Figure 34. DAC Transition Band (Detail)
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CS42L55 10.PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dB signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 dBFS and -20 dBFS for the analog input and 0 dB and -20 dB for the analog output as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. HP to ADC Isolation A measure of crosstalk between the headphone amplifier and the ADC inputs. Measured for each channel at the ADC's output with no signal to the input and a full-scale signal applied to the headphone amplifier with a 16 or 10 k load. Units in decibels. Output Offset Voltage Describes the DC offset voltage present at the amplifier's output during a MUTE state. When measuring the offset out the line amplifier, the line amplifier is ON while the headphone amplifier is OFF; when measuring the offset out the headphone amplifier, the headphone amplifier is ON while the line amplifier is OFF. The offset observed at the output of the HP/Line amplifiers is a result of the non-infinite CMRR of the output amplifier that exists due to CMOS process limitations and is proportional to the analog volume settings. AC Load Resistance and Capacitance RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal.
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CS42L55 11.PACKAGE DIMENSIONS
(Unless otherwise specified, linear tolerance is 0.05 mm, and angular tolerance is 2 deg.)
36L QFN (5 X 5 mm BODY) PACKAGE DRAWING (Note 2)
P2 D b 1.50 REF e P1
PIN #1 CORNER
P2 P1
1.50 REF
Pin #1 IDENTIFIER LASER MARKING
E
E2
A1 D2 A L
Dim
A A1 b e D E D2 E2 L P1 P2
MIN
0.01773 0.00000 0.00591 0.19503 0.19503 0.13593 0.13593 0.01379 0.00985 0.00985
INCHES NOM
MAX
0.0197 0.00197 0.00985 0.19897 0.19897 0.13987 0.13987 0.01773 0.01379 0.01379
MIN
0.45 0.00 0.15 4.95 4.95 3.45 3.45 0.35 0.25 0.25
MILLIMETERS NOM
0.20 0.40 REF 5.00 5.00 3.50 3.50 0.40 0.30 0.30
NOTE MAX
0.50 0.05 0.25 5.05 5.05 3.55 3.55 0.45 0.35 0.35 1,3 1,3 1,3,4 1,3 1,3 1,3 1,3 1,3 1,3 1,3 1,3
0.00788 0.01576 0.1970 0.1970 0.1379 0.1379 0.1576 0.01182 0.01182
JEDEC #: MO-220 Controlling Dimension is Millimeters. 1. Controlling dimensions are in millimeters. 2. Unless otherwise specified tolerance: Linear 0.05 mm, Angular 2 deg. 3. Dimensioning and tolerances per ASME Y 14.5M-1994. 4. Dimension lead width applies to the plated terminal and is measured 0.15 mm and 0.30 mm from the terminal tip.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance 2 Layer Board 4 Layer Board
Symbol
JA JA
Min
-
Typ
68 28
Max
-
Units
C/Watt C/Watt
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CS42L55 12.ORDERING INFORMATION
Product Description Package Ultra Low Power, Stereo CS42L55 CODEC w/ Class H HP Amp 36L-QFN for Portable Apps CDB42L55 CS42L55 Evaluation Board Pb-Free YES No Grade Temp Range Container Order # Rail CS42L55-CNZ Tape & Reel CS42L55-CNZR CDB42L55
Commercial -40C to +85C -
13.REFERENCES
1. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
14.REVISION HISTORY
Revision
F1 Initial Release
Changes
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor.
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